Metal Gate Stack Barrier Layout for Spacer Etch Protection
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Solution Overview
Problem
In the semiconductor industry, the fabrication of high-k metal transistors faces issues such as over-etching and undercut during the formation of spacers, leading to erosion of the high-k dielectric layer and bottom barrier metal, which affects device performance.
Innovation Solution
A method involving the formation of a substrate with defined regions, a bottom barrier metal layer, a work function metal layer, and a diffusion barrier layer, where the thickness of the bottom barrier metal layer on one region is less than on another, and a diffusion barrier layer is formed to contact the work function metal layer and bottom barrier metal layer, ensuring proper coverage and reducing etching-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional polysilicon gate is used, then fabrication process is simple, but device performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional polysilicon to metal materials with different work functions. By selecting metals such as titanium nitride, tantalum nitride, or tungsten with specific work function values, the gate can achieve better electrical characteristics without suffering from boron penetration and depletion effects, thus improving device performance while maintaining fabrication feasibility
Solution Approach 2:
The patent employs composite gate structures combining multiple materials: a bottom barrier metal layer (such as titanium nitride or tantalum nitride) deposited on the high-k dielectric layer, and a work function metal layer (such as tungsten or molybdenum) deposited on top. This composite structure provides both excellent interface characteristics and controllable work function, resolving the contradiction between manufacturing simplicity and device performance
2Productivity
If high-k metal transistor is fabricated with conventional process, then production efficiency is maintained, but over-etching and undercut occur causing erosion of high-k dielectric layer and bottom barrier metal
Solution Approach 1:
The patent applies a thin diffusion barrier layer (such as silicon nitride or silicon oxide) on the work function metal layer before spacer formation. This preliminary protective layer prevents etching gas from reaching and eroding the bottom barrier metal and high-k dielectric layer during spacer etching processes, thereby maintaining manufacturing precision without reducing production efficiency
Solution Approach 2:
The diffusion barrier layer serves as an intermediary protective layer between the work function metal layer and the underlying sensitive structures (bottom barrier metal and high-k dielectric layer). This intermediary layer effectively blocks harmful etching effects while allowing the fabrication process to proceed with standard productivity levels
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.