Metal Gate Fill Using Bottom-Up Electroless Plating

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Solution Overview

Problem

Traditional deposition techniques for gate electrode fill in nano-FET manufacturing often result in voids or seams due to high aspect ratios, inhibiting the designed operation of the gate in nano-FETs.

Innovation Solution

The use of electroless plating with accelerators and suppressors in an electrochemical bath to achieve a bottom-up deposition method, which fills the recess from the bottom up rather than depositing on all surfaces simultaneously, reducing voids and seams.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional deposition techniques are used for gate electrode fill, then the deposition process is simple and fast, but voids or seams form due to high aspect ratios

Engineering Contradiction:
Improvefill completenessVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by first depositing a thin conformal layer of metal material across all surfaces before performing selective removal. This initial uniform deposition ensures complete coverage, and subsequent selective removal at the top surface creates the desired gate electrode structure without voids or seams in high-aspect-ratio regions

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The deposition process is segmented into distinct stages: (1) conformal deposition of metal material across all surfaces, (2) selective removal of excess material at the top surface, and (3) formation of the final gate electrode structure. This segmentation allows precise control over fill completeness while managing process complexity

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If conformal deposition is used on all surfaces simultaneously, then the process is efficient, but voids form in high-aspect-ratio openings

Engineering Contradiction:
Improvedeposition uniformityVSAvoidgate operation
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent uses preliminary conformal deposition to uniformly coat all surfaces including high-aspect-ratio openings, ensuring complete fill without voids. The uniform deposition serves as a preliminary step that guarantees reliability, followed by selective removal to achieve the final structure

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

After complete conformal deposition, the patent extracts or removes the excess metal material from the top surface selectively. This extraction process removes only the unnecessary portions while preserving the complete fill in high-aspect-ratio regions, ensuring both deposition uniformity and gate operation reliability

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively fills the recesses without voids or seams, enhancing the operational integrity of the gate electrode in nano-FETs by ensuring complete deposition in high-aspect-ratio openings.

Implementation Method 1

The use of electroless plating with accelerators and suppressors in an electrochemical bath to achieve a bottom-up deposition method

Methodology Applied
Scientific EffectElectroless plating: Electrodeposition

Data Source

PatentUS20240387690A1Electroless Plating Method for Metal Gate Fill
Publication Date: 2024.11.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240387690A1 patent drawing
  • US20240387690A1 patent drawing
  • US20240387690A1 patent drawing

AI summary

Embodiments utilize an electro-chemical process to deposit a metal gate electrode in a gate opening in a gate replacement process for a nanosheet FinFET device. Accelerators and suppressors may be used to achieve a bottom-up deposition for a fill material of the metal gate electrode.