Metal Gate Patterning Etchant for Low Boundary Loss
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to minimize metal gate boundary loss during processing to allow for closer transistor placement and increased transistor density in FinFET and multi-gate devices like gate-all-around FETs.
Innovation Solution
A method using a wet etching process with a specific etchant comprising an organic acid or base and an oxidant, minimizing penetration into the mask to reduce lateral dimension, thereby preserving the masked region and allowing for closer transistor spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional wet etching processes are used to remove material layers, then etching efficiency is improved, but mask penetration increases causing lateral dimension loss and reduced manufacturing precision
Solution Approach 1:
The patent modifies the chemical composition parameters of the etchant by incorporating specific additives that alter the etching mechanism. These compositional changes enable the etchant to selectively react with the material layer while being blocked by the mask, thereby maintaining high etching efficiency without causing lateral dimension loss or mask penetration.
2Productivity
If transistor spacing is reduced to increase density, then transistor density improves, but metal gate boundary loss increases reducing reliability
Solution Approach 1:
The patent converts the potential harm of mask penetration into a benefit by using the etchant composition to define precise gate boundaries. The controlled etching process actually enhances boundary definition by removing material cleanly at the mask edge, preventing metal gate boundary loss and improving reliability while enabling reduced transistor spacing.
3Manufacturing precision
If etchant penetration into mask is minimized, then lateral dimension loss is reduced improving manufacturing precision, but etching completeness may be compromised
Solution Approach 1:
The patent adjusts the etchant composition parameters to achieve optimal balance between precision and completeness. By incorporating specific chemicals in controlled concentrations, the etchant maintains high reactivity toward the material layer for complete removal while the mask acts as an effective barrier, preventing lateral penetration and ensuring accurate dimensional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces metal gate boundary loss, enabling a 5 to 10 nm reduction in spacing between transistors, leading to a 15 to 20% increase in transistor density and improved critical dimension.
Implementation Method 1
performing an etch process with an etchant to remove the material layer from the uncovered region, wherein the etchant penetrates the mask to a dimension of less than 5 nm
Data Source
AI summary
Semiconductor structures and methods for fabricating semiconductor structures are provided. A method includes forming a first structure and a second structure over a substrate; forming a material layer over each structure; covering the first structure with a mask, wherein the second structure is uncovered; and performing an etch process to remove the material layer from the second structure, wherein the etch process is performed with an etchant comprising a first component and an oxidant, and wherein the first component is selected from an organic acid having a molecular weight of from 14 to 104 g/mol and an organic base having a molecular weight of from 20 to 104 g/mol.