Metal Gate Boundary Layout for Multi-Threshold Transistor Scaling
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming transistors with different thresholds using multiple layers of work-function metals, which complicates the process and increases difficulty due to gate opening limitations, especially in replacement-metal-gate processes, where PFETs and NFETs often share metals, leading to issues with pinch-off and void formation during organic planarization.
Innovation Solution
A method involving the truncation of work-function metals at specific boundaries between adjacent transistors allows for the formation of an organic planarization layer that can fill gaps without creating voids, enabling the manufacturing of transistors with varying thresholds by selectively etching and depositing additional work-function metals to ensure proper layer alignment and coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple layers of work-function metals are used to form transistors with different thresholds, then threshold control is improved, but gate opening is narrowed and manufacturing difficulty increases
Solution Approach 1:
The patent applies segmentation by dividing the work-function metal structure into multiple truncated layers. Each layer is selectively removed at specific boundaries to create discrete gate openings for different transistor types. This segmentation allows multiple work-function metals to be used without completely closing the gate opening, as each truncated layer creates a controlled opening path.
Solution Approach 2:
The patent implements local quality by applying different truncation patterns to different regions of the work-function metal layers. Specifically, the first work-function metal is truncated at a first boundary while the second work-function metal is truncated at a second boundary, creating locally optimized structures for PFET and NFET regions. This allows each transistor type to have its gate opening precisely controlled in its specific location.
2Ease of manufacture
If multiple layers of work-function metals are shared between PFET and NFET, then manufacturing process is simplified, but pinch-off and void formation occur during organic planarization
Solution Approach 1:
The patent applies preliminary action by pre-truncating the work-function metal layers at defined boundaries before the organic planarization step. This preliminary truncation creates sufficient gap width in advance, ensuring that the organic planarization layer can flow and fill the gap completely without pinching off. By preparing the gap structure beforehand, the patent prevents void formation during subsequent planarization while maintaining the shared metal structure benefits.
3Reliability
If work-function metals are truncated at boundaries between transistors, then organic planarization layer can fill gaps without voids, but additional etching and deposition steps are required
Solution Approach 1:
The patent merges multiple operations into integrated process steps. The truncation of work-function metals is combined with the organic planarization step, where the same boundary definitions serve both the metal truncation and the gap formation for planarization. Additionally, the selective etching and deposition of work-function metals are merged with the threshold adjustment process, reducing the total number of discrete steps while achieving multiple objectives simultaneously.
Data Source
AI summary
Embodiments of present invention provide a method of forming a transistor structure. The method includes receiving a first and a second gate region of a first and a second transistor, the second transistor being adjacent to the first transistor; forming a first work-function metal surrounding the first gate region; truncating the first work-function metal at a first boundary between the first transistor and the second transistor; forming one or more work-function metals surrounding the first gate region; truncating the one or more work-function metals at a second boundary between the first boundary and the second transistor; and forming another work-function metal surround the first and second gate regions. A transistor structure formed thereby is also provided.