Dual Work Function Metal Gate Cap Layers for Leakage Control
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Solution Overview
Problem
As semiconductor devices shrink, thinner gate insulation layers lead to leakage current, and using high-k materials can cause Fermi-level pinning and threshold voltage increases, while metal gates are affected by high-temperature processes, impacting device performance.
Innovation Solution
The method involves forming dual work function metal gates with different cap layers under identical metal layers, allowing adjustment of work functions through cap layer materials and thicknesses, and integrating with strain engineering and current fabrication processes to enhance competitiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a high-k material is used for forming the gate insulation layer to reduce leakage current, then the leakage current is reduced, but the gate including polysilicon reacts with the high-k material to generate Fermi-level pinning, increasing the threshold voltage and affecting device performance
Solution Approach 1:
A cap layer is introduced as an intermediary between the polysilicon gate and the high-k gate insulation layer. This cap layer prevents direct contact and chemical reaction between the polysilicon and high-k material, thereby eliminating Fermi-level pinning and threshold voltage shifts while maintaining the low leakage current benefits of the high-k material.
2Reliability
If a metal layer is used as the gate to avoid Fermi-level pinning, then the threshold voltage stability is improved, but the work function of the metal layer shifts due to high temperature in subsequent high-temperature processes, affecting device performance
Solution Approach 1:
The cap layer serves as a protective intermediary that shields the metal gate from exposure to high-temperature processing environments. By preventing direct interaction between the metal and the high-temperature process, the cap layer stabilizes the metal's work function and prevents unwanted chemical reactions or diffusion that would otherwise occur during subsequent fabrication steps.
3Length of moving object
If the gate dimension is reduced to maintain device performance as device size shrinks, then the device scaling is achieved, but the gate insulation layer thickness must be reduced accordingly, increasing leakage current
Solution Approach 1:
The invention changes the dielectric constant parameter of the gate insulation layer by using high-k material instead of conventional silicon oxide. This parameter change allows the gate insulation layer to maintain sufficient electrical isolation performance even at reduced thicknesses required for scaled-down device dimensions, thereby preventing excessive leakage current while enabling continued device scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents work function shifts and Fermi-level pinning, maintaining device performance while being compatible with strain engineering and existing fabrication processes, thus enhancing competitiveness.
Implementation Method 1
the gate including polysilicon may react with the high-k material to generate a Fermi-level pinning, so that the threshold voltage is increased
Implementation Method 2
a metal layer and a polysilicon layer are sequentially formed on the first and second cap layers
Data Source
AI summary
A semiconductor device and a method of fabricating the same are described. A substrate having a PMOS area and an NMOS area is provided. A high-k layer is formed on the substrate. A first cap layer is formed on the high-k layer in the PMOS area, and a second cap layer is formed on the high-k layer in the NMOS area, wherein the first cap layer is different from the second cap layer. A metal layer and a polysilicon layer are sequentially formed on the first and second cap layers. The polysilicon layer, the metal layer, the first cap layer, the second cap layer and the high-k layer are patterned to form first and second gate structures respectively in the PMOS and NMOS areas. First source/drain regions are formed in the substrate beside the first gate structure. Second source/drain regions are formed in the substrate beside the second gate structure.