Metal Gate Modulator Stack to Prevent Silicon Cap Oxidation
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Solution Overview
Problem
The poly-depletion effect in conventional polysilicon gates increases the effective gate dielectric thickness, making it difficult to generate an inversion layer in semiconductor devices, and existing metal gate formation processes face challenges in reducing oxidation and improving reliability.
Innovation Solution
The formation of metal gates with a work-function layer, a capping layer, and a silicon layer, where these layers are in-situ deposited without a vacuum break to reduce oxidation and improve the reliability of the gate dielectric, and the use of a glue layer to prevent oxidation of the silicon capping layer, allowing for a thinner glue layer and reduced gate contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional polysilicon gates are used, then the gate structure is simple to form, but the poly-depletion effect increases the effective gate dielectric thickness, making it difficult to generate an inversion layer
Solution Approach 1:
The patent changes the material parameter of the gate from polysilicon to metal (such as tungsten, cobalt, or titanium nitride), which fundamentally alters the electrical characteristics and eliminates the poly-depletion effect. This material substitution allows for proper inversion layer generation while maintaining manufacturability through established metal deposition and CMP processes
2Adaptability or versatility
If metal gates with multiple layers are formed using conventional processes, then the gate structure can meet different requirements of NMOS and PMOS devices, but the process complexity increases with multiple deposition and CMP steps
Solution Approach 1:
The patent segments the gate structure into distinct functional layers (metal gate layer, work function layer, capping layer) with each layer serving a specific purpose. The metal gate layer provides conductivity, the work function layer tunes the threshold voltage for different device types (NMOS/PMOS), and the capping layer provides protection. This segmentation allows independent optimization of each layer while maintaining overall process efficiency
Solution Approach 2:
The patent employs a universal metal gate structure that can serve both NMOS and PMOS devices through selective work function layer materials or thickness variations. The same basic process flow (deposition of metal layer, work function layer, and capping layer followed by CMP) is used for both device types, reducing process complexity while maintaining adaptability
3Reliability
If the silicon capping layer is exposed to oxygen during processing, then the oxidation of the silicon layer increases, but this leads to increased gate contact resistance and reduced reliability
Solution Approach 1:
The patent applies a thin layer of titanium nitride (TiN) as a protective capping layer over the silicon capping layer before any oxygen exposure can occur. This preliminary protective action prevents oxidation of the silicon layer throughout subsequent processing steps, eliminating the need for complex atmospheric control measures and directly preventing the harmful oxidation effect
4Object-affected harmful factors
If a thicker glue layer is used to prevent oxidation, then the oxidation protection is improved, but the gate contact resistance increases
Solution Approach 1:
The patent changes the material composition of the capping layer from pure silicon to a composite structure with titanium nitride (TiN) added. TiN provides superior oxidation resistance compared to silicon alone, allowing the use of a thinner capping layer thickness while achieving the same or better oxidation protection. This material parameter change directly reduces gate contact resistance while maintaining protection against oxidation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate contact resistance by preventing silicon capping layer oxidation, improves the reliability of the gate dielectric, and increases the diffusion of fluorine into high-k dielectric layers, enhancing the reliability of the transistors.
Implementation Method 1
a work-function layer, a capping layer, and a silicon layer are in-situ formed, with no vacuum break between the formation processes
Implementation Method 2
a titanium nitride layer between the work-function layer and the silicon layer
Data Source
AI summary
A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.