Metal Gate Capping Layer Doping for Interface Passivation
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in the manufacturing processes, including the integration of metal gates and channels, where issues such as oxygen vacancies, silicon dangling bonds, and weak silicon-hydrogen bonding degrade performance.
Innovation Solution
The implementation of a divergent ion beam for implanting dopants into a capping layer over a metal gate and high-k dielectric layer, followed by a second anneal process to drive these dopants into the semiconductor fin, interfacial layer, and high-k dielectric layer, creating concentration gradients that enhance interface passivation and reduce oxygen vacancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ion beam implantation is used to dope semiconductor fins, then doping can be achieved, but oxygen vacancies and silicon dangling bonds remain causing degraded device performance
Solution Approach 1:
The method applies preliminary action by first forming a capping layer over the high-k dielectric layer before ion beam implantation. This capping layer serves as a protective barrier that prevents oxygen vacancies and silicon dangling bonds from forming during the doping process, thereby maintaining interface quality while achieving the desired doping effect in the semiconductor fin.
Solution Approach 2:
The capping layer acts as an intermediary between the ion beam and the high-k dielectric layer/semiconductor fin interface. By introducing this intermediate layer, the harmful direct interaction between the ion beam and the interface is avoided, preventing the formation of oxygen vacancies and silicon dangling bonds while still allowing dopants to reach the semiconductor fin through controlled diffusion.
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated, but manufacturing process challenges increase
Solution Approach 1:
The method addresses manufacturing challenges at reduced feature sizes by changing the doping parameters - specifically using a two-step process with divergent ion beam angles (e.g., ±10 degrees) and controlled annealing temperatures. This allows precise dopant distribution in scaled devices while maintaining interface quality, enabling continued integration density improvement without proportionally increasing process complexity.
3Productivity
If dopants are implanted directly into the semiconductor fin, then doping efficiency can be high, but interface damage and oxygen vacancies increase
Solution Approach 1:
The capping layer serves as an intermediary that enables dopant transport to the semiconductor fin while protecting the sensitive interfaces. During annealing, dopants diffuse through the capping layer to reach the fin, achieving high doping efficiency, while the capping layer prevents direct ion beam damage and oxygen vacancy formation at the high-k dielectric/fin interface.
Solution Approach 2:
The method replaces direct mechanical ion beam impact on the semiconductor fin with a thermal diffusion process. Instead of implanting dopants directly into the fin (mechanical impact), dopants are first deposited in the capping layer and then transported to the fin through thermal diffusion during annealing, eliminating interface damage while maintaining doping efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves channel resistance in semiconductor devices by strengthening the interface between semiconductor fins and dielectric layers, reducing oxygen vacancies, and achieving more conformal doping, thereby enhancing the performance of metal gate and channel structures.
Implementation Method 1
implanting dopants into a capping layer over a metal gate and high-k dielectric layer, followed by a second anneal process to drive these dopants into the semiconductor fin
Implementation Method 2
a second anneal process to drive these dopants into the semiconductor fin, interfacial layer, and high-k dielectric layer, creating concentration gradients
Data Source
AI summary
A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.