Metal Gate Capping Layer for FinFET Oxidation Control

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Solution Overview

Problem

In the formation of Metal-Oxide-Semiconductor (MOS) devices, particularly in Fin Field-Effect Transistors (FinFETs), the challenge is to prevent the oxidation of metal gates during subsequent annealing processes, which can lead to undesirable shifts in the threshold voltage of the transistors.

Innovation Solution

A dielectric capping layer, free from oxygen and capable of blocking oxygen diffusion, is deposited over the metal gates before the formation of an oxygen-containing inter-layer dielectric. This capping layer prevents the underlying metal gates from oxidizing during annealing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an oxygen-containing inter-layer dielectric is deposited directly over metal gates, then the inter-layer dielectric can be formed, but the metal gates oxidize during annealing processes causing threshold voltage shifts

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidmetal gate oxidation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An oxygen-blocking dielectric capping layer is deposited between the metal gate and the oxygen-containing inter-layer dielectric. This intermediate layer acts as a barrier that prevents oxygen diffusion from the inter-layer dielectric to the metal gate during annealing processes, thereby eliminating the oxidation problem while allowing both components to coexist.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The oxygen-blocking dielectric capping layer is applied in advance before the oxygen-containing inter-layer dielectric is deposited. This preliminary protective action prevents the harmful oxidation effect from occurring during subsequent annealing processes, stabilizing the threshold voltage before the problem can manifest.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If a dielectric capping layer is deposited over metal gates, then oxidation is prevented, but the device structure becomes more complex

Engineering Contradiction:
Improvemetal gate oxidation resistanceVSAvoidlayer structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dielectric capping layer serves multiple functions: it acts as an oxygen diffusion barrier to prevent metal gate oxidation, provides a planarized surface for subsequent inter-layer dielectric deposition, and can serve as an etch stop layer during fabrication processes. By combining multiple functions in a single layer, the overall device complexity is minimized while achieving reliable oxidation protection.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of an oxygen-blocking dielectric capping layer effectively reduces the oxidation of metal gate electrodes, thereby stabilizing the threshold voltage of FinFETs and improving their performance.

Implementation Method 1

A dielectric capping layer, free from oxygen and having a capability of blocking oxygen diffusion, is deposited over and contacting the metal gates

Methodology Applied
Scientific EffectOxygen diffusion blocking: Diffusion Barrier

Implementation Method 2

This capping layer prevents the underlying metal gates from oxidizing during annealing processes

Methodology Applied
Scientific EffectOxidation prevention: Oxidation

Data Source

PatentUS12293916B2Surface oxidation control of metal gates using capping layer
Publication Date: 2025.05.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12293916B2 patent drawing
  • US12293916B2 patent drawing
  • US12293916B2 patent drawing

AI summary

A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.