Metal Gate Capping Layer for Lower FinFET Gate Resistance
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Solution Overview
Problem
The challenge of reducing gate resistance in nanosheet field-effect transistors (NS FETs) and FinFETs has not been adequately addressed, particularly due to the reduced volume available for gap-filling during the formation of metal gate structures, leading to higher gate resistance (Rg) in semiconductor devices.
Innovation Solution
A method involving the formation of a metal capping layer over the metal gate structure, using a deposition process such as ALD with tungsten hexafluoride (WF6) to reduce resistance, combined with a glue layer to enhance adhesion and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is scaled down to increase functional density, then the number of interconnected devices per chip area increases, but the gate resistance increases due to reduced volume available for gap-filling
Solution Approach 1:
The patent applies local quality by forming a metal capping layer specifically at the gate contact region where low resistance is critical. This localized modification targets the high-resistance area without changing the overall gate structure, providing reduced gate resistance precisely where needed while maintaining the scaled-down dimensions for high functional density.
Solution Approach 2:
The patent uses composite materials by combining the existing metal gate structure with an additional metal capping layer. This composite approach creates a multi-layer gate structure where the capping layer provides low-resistance contact properties, effectively reducing gate resistance while preserving the benefits of scaled-down gate dimensions for increased functional density.
2Area of moving object
If the gate dimensions are reduced to increase device integration, then more devices can be placed on chip area, but the volume available for gap-filling decreases leading to higher resistance
Solution Approach 1:
The metal capping layer is applied locally at the gate contact region rather than throughout the entire gate structure. This localized approach maintains the reduced gate dimensions for high chip area utilization while providing the low-resistance property specifically where the gate contact is made, addressing the resistance issue without compromising integration density.
Solution Approach 2:
The patent addresses the volume limitation by adding a layer in the vertical dimension. The metal capping layer is deposited over the gate structure, utilizing the vertical dimension to provide additional conductive material without increasing the lateral footprint, thus maintaining high chip area utilization while reducing resistance through the added dimensional capacity.
3Ease of manufacture
If existing methods are used to form metal gate structures at reduced length scales, then fabrication processes can be maintained, but gate resistance remains high due to insufficient gap-filling volume
Solution Approach 1:
The metal capping layer is formed as a preliminary step before final gate contact formation. This preliminary action prepares the gate structure with a low-resistance surface layer in advance, ensuring that when the gate contact is subsequently formed, the resistance is already minimized, thereby maintaining fabrication process continuity while achieving low gate resistance.
Solution Approach 2:
The patent employs composite materials by integrating a metal capping layer with the existing metal gate structure. This composite structure combines the benefits of the original gate material with the low-resistance properties of the capping layer material, allowing existing fabrication processes to be maintained while achieving the desired low gate resistance through material composition enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a metal capping layer significantly reduces gate resistance, improving the conductivity and performance of semiconductor devices by ensuring effective gap-filling and minimizing seam formation.
Implementation Method 1
A method for forming a metal capping layer over the metal gate structure using a tungsten-containing precursor, such as WF6, through an atomic layer deposition (ALD) process
Implementation Method 2
while residual fluorine atoms improve the reliability of the device
Data Source
AI summary
A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.