Replacement Metal Gate Process With Carbon-Implanted Zero ILD
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Solution Overview
Problem
The existing methods for forming metal gates in semiconductor devices face issues with poor film quality of zero interlayer dielectrics due to high etching rates, leading to uneven surfaces and compromised CMP process windows, which affect device performance and yield.
Innovation Solution
A method involving carbon ion implantation to form a carbon-doped zero interlayer dielectric surface layer, combined with dry and wet etching, to reduce the etching rate and protect the interlayer dielectric during subsequent etching steps, ensuring better surface flatness and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If FCVD process is used to form zero interlayer dielectric, then via-hole filling is facilitated, but film quality deteriorates resulting in poor zero interlayer dielectric performance
Solution Approach 1:
A carbon-doped surface layer is introduced as an intermediary between the FCVD oxide and the etching process. This intermediate layer modifies the etching characteristics, reducing the etching rate and preventing direct exposure of the underlying FCVD oxide, thereby protecting it from excessive etching damage while maintaining the filling capability.
Solution Approach 2:
The etching rate parameter is modified by introducing carbon doping into the oxide surface layer. This changes the chemical composition and physical properties of the surface, transforming it from a high-etching-rate material to a low-etching-rate protective layer, thus resolving the contradiction between filling capability and performance.
2Reliability
If ISSG oxide layer is removed from core region, then input/output region protection is achieved, but FCVD oxide layer loss increases causing uneven surface
Solution Approach 1:
The carbon-doped surface layer is formed in advance before the ISSG oxide removal process. This preliminary action creates a protective barrier that prevents excessive loss of the FCVD oxide layer during subsequent etching steps, thereby maintaining surface uniformity while still allowing ISSG oxide removal in the core region.
Solution Approach 2:
The carbon-doped surface layer serves as a cushioning layer that absorbs and mitigates the harmful effects of etching on the FCVD oxide. By placing this protective layer beforehand, the patent prevents the uneven surface formation that would otherwise occur during ISSG oxide removal.
3Manufacturing precision
If carbon ion implantation is performed on zero interlayer dielectric, then etching rate is reduced and surface flatness is improved, but process complexity increases
Solution Approach 1:
The carbon ion implantation process is merged with the existing oxide formation process. Instead of treating them as separate steps, the carbon doping is integrated into the oxide deposition or annealing process, thereby reducing overall process complexity while achieving the desired surface flatness and etching rate reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integrity of the zero interlayer dielectric, improving the CMP process window and subsequent metal gate filling, thereby enhancing device performance and yield.
Implementation Method 1
implanting carbon into a surface region of the zero interlayer dielectric by means of carbon ion implantation
Data Source
AI summary
The present application discloses a method for manufacturing a metal gate, comprising: step 1, providing a semiconductor substrate on which dummy polysilicon gates are formed, wherein a first gate dielectric layer is formed at the bottom of the dummy polysilicon gates, and a spacing region between the dummy polysilicon gates is filled with a zero interlayer dielectric; step 2, removing the dummy polysilicon gates, comprising: step 21, performing first dry etching to remove a part of the thickness of the dummy polysilicon gate; step 22, performing carbon ion implantation to form a carbon containing surface region of the zero interlayer dielectric; and step 23, performing second wet etching to fully remove the remaining dummy polysilicon gates; step 3, performing third etching to remove the first gate dielectric layer; and step 4, forming a second gate dielectric layer and a metal gate.