Metal-Gate CMOS Device with Embedded Epitaxial Layers
Solution Overview
Problem
The integration of dual work-function metal gates in CMOS devices is complex due to the need for precise control of materials and processes, particularly in achieving complementary gate work functions for NMOS and PMOS devices, which complicates the fabrication process and increases costs.
Innovation Solution
The method involves forming embedded SiGe and SiC epitaxial layers in specific regions of the substrate, using a sequence of dummy gate structures, spacers, and chemical mechanical polishing to simplify the fabrication steps and reduce complexity, incorporating high-k gate dielectrics and metal gates with suitable work functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual work-function metal gates are integrated in CMOS devices, then complementary gate work functions for NMOS and PMOS are achieved, but the fabrication process complexity increases
Solution Approach 1:
The patent divides the gate structure into separate NMOS and PMOS regions, each with its own dummy gate structure and embedded epitaxial layer. This segmentation allows independent formation of different work function metals in adjacent regions, achieving complementary gate characteristics while using a unified process flow that reduces overall fabrication complexity.
Solution Approach 2:
The patent applies different materials and processes to different regions of the substrate. Specifically, SiGe embedded epitaxial layers are formed in PMOS regions while SiC embedded epitaxial layers are formed in NMOS regions. This local differentiation enables precise control of work functions for each transistor type without requiring complex global process modifications.
2Reliability
If dual work-function metal gates are integrated in CMOS devices, then complementary gate work functions for NMOS and PMOS are achieved, but manufacturing costs increase
Solution Approach 1:
The patent merges the formation of different work function metals into a single integrated process flow. By using sequential embedded epitaxial growth with region-specific masking, both SiGe and SiC layers are formed in the same fabrication sequence, eliminating the need for separate process modules and reducing manufacturing costs despite the added functionality.
Solution Approach 2:
The patent employs a universal dummy gate structure and embedded epitaxial process that serves multiple functions: it defines the gate region, controls the work function through material selection, and enables subsequent metal gate formation. This multi-functional approach reduces the number of specialized process steps required, thereby lowering manufacturing costs.
3Ease of manufacture
If polysilicon is used as gate electrode, then fabrication is simpler, but poly-depletion effect occurs
Solution Approach 1:
The patent extracts the problematic polysilicon material from the gate electrode and replaces it with metal layers formed through embedded epitaxial processes. By removing polysilicon and using metals such as TiN, TaN, or W with appropriate work functions, the poly-depletion effect is eliminated while maintaining fabrication simplicity through the use of standard semiconductor processing techniques.
Solution Approach 2:
The patent changes the fundamental parameter of gate electrode material from polysilicon to metal. This material substitution fundamentally alters the electrical characteristics by eliminating the depletion effect inherent in polysilicon, while the embedded epitaxial process ensures the metal layers are formed with precise thickness and composition control.
4Reliability
If metal-gate electrodes are used, then sheet resistance is reduced, but thermal stability control becomes more difficult
Solution Approach 1:
The patent employs composite gate electrode structures consisting of multiple metal layers with different properties. The embedded epitaxial process forms these composite structures with precise control over layer composition, thickness, and crystalline orientation. This composite approach allows optimization of both electrical properties (low sheet resistance) and thermal stability by selecting materials with complementary characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the CMOS fabrication process, reduces manufacturing costs, and enhances the integration of dual work-function metal gates, improving thermal stability and reducing the poly-depletion effect, while providing wider material choices for high-K gate dielectrics.
Implementation Method 1
A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.
Data Source
AI summary
A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.