Metal Gate Structure CMOS Device Isolation
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Solution Overview
Problem
In integrated circuit fabrication, particularly in CMOS technology, the 'gate last' process faces challenges in achieving perfect isolation between transistors due to unwanted recesses in the inter-layer dielectric layer after etching, which can lead to electrical shorting and device failure as feature sizes shrink.
Innovation Solution
A method for fabricating a CMOS semiconductor device with a metal gate structure involves forming a substrate with isolation regions, gate dielectric layers, and dummy gate electrodes, followed by precise etching and chemical mechanical polishing to minimize ILD layer recesses, ensuring perfect isolation and preventing metal accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate last process is used to improve device performance with decreased feature sizes, then device performance is improved, but unwanted recesses are generated in the ILD layer after etching dummy strips, leading to increased likelihood of electrical shorting and device failure
Solution Approach 1:
The patent applies preliminary action by performing Chemical Mechanical Polishing (CMP) on the ILD layer before etching the dummy strips. This pre-polishing step creates a planarized surface that compensates for the recesses that will later form during dummy strip removal, ensuring that the final ILD surface remains planar and prevents metal accumulation in recess areas.
Solution Approach 2:
The patent implements beforehand cushioning by depositing an additional layer of ILD material over the etched dummy strip regions after dummy strip removal. This extra ILD material acts as a cushion or fill that compensates for the recesses created during etching, ensuring complete isolation between transistors and preventing electrical shorting.
2Productivity
If gate length and spacing between devices are decreased to improve integration density, then device integration is improved, but achieving perfect isolation between neighboring transistors becomes more difficult due to ILD recesses
Solution Approach 1:
The patent applies preliminary action by performing Chemical Mechanical Polishing (CMP) on the ILD layer before etching the dummy strips. This pre-polishing step creates a planarized surface that compensates for the recesses that will later form during dummy strip removal, ensuring that the final ILD surface remains planar and prevents metal accumulation in recess areas.
Solution Approach 2:
The patent implements beforehand cushioning by depositing an additional layer of ILD material over the etched dummy strip regions after dummy strip removal. This extra ILD material acts as a cushion or fill that compensates for the recesses created during etching, ensuring complete isolation between transistors and preventing electrical shorting.
3Ease of manufacture
If wet/dry etching is used to remove dummy strips in gate last process, then dummy strip removal is achieved, but recesses are generated in the ILD layer that can become receptacles for metals during subsequent processing
Solution Approach 1:
The patent applies preliminary action by performing Chemical Mechanical Polishing (CMP) on the ILD layer before etching the dummy strips. This pre-polishing step creates a planarized surface that compensates for the recesses that will later form during dummy strip removal, ensuring that the final ILD surface remains planar and prevents metal accumulation in recess areas.
Solution Approach 2:
The patent converts the harmful effect of ILD recesses into a beneficial outcome by using CMP to intentionally create a slightly recessed profile before dummy strip removal. This pre-created relief allows the subsequent etching to produce a planar final surface, and any remaining minor recesses are filled with additional ILD material, transforming the potential harm into a controlled process advantage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by eliminating ILD layer recesses, reducing the likelihood of electrical shorting and device failure, and achieving improved isolation between neighboring transistors.
Implementation Method 1
chemical mechanical polishing to minimize ILD layer recesses
Data Source
AI summary
A semiconductor device includes a substrate with an isolation region surrounding a P-active region and an N-active region, a first gate electrode comprising a first metal composition over the N-active region, and a second gate electrode with a center portion over the P-active region and an endcap portion over the isolation region. The endcap portion includes a first metal composition, and the center portion includes a second metal composition different from the first metal composition, and the center portion and the endcap portion do not overlap. An inner sidewall of the endcap portion is substantially aligned with a sidewall of the isolation region.