Integrated Metal Gate CMOS Devices for Threshold Voltage Control
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Solution Overview
Problem
As CMOS technology scales to smaller dimensions, achieving precise threshold voltage control becomes challenging due to complex device structures and impurity scattering, leading to performance degradation, especially in finFET, nanosheet, and nanowire devices, where channel doping is necessary to adjust threshold voltage, impacting mobility and device performance.
Innovation Solution
The method involves forming different gate stacks on a single substrate by depositing various metal layers and work function metals on channel regions, allowing for independent control of threshold voltages without the need for channel doping, thereby enhancing device performance by eliminating the performance degradation associated with channel doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If channel doping is used to adjust threshold voltage in finFET, nanosheet, and nanowire devices, then threshold voltage control is achieved, but mobility is degraded and device performance is impacted
Solution Approach 1:
The patent changes the parameter for threshold voltage control from channel doping concentration to gate metal work function. By selecting different metal materials (e.g., titanium nitride, tungsten, cobalt) with distinct work functions, the threshold voltage can be precisely tuned without introducing impurities into the channel, thereby avoiding mobility degradation and maintaining high device performance
Solution Approach 2:
The patent extracts the threshold voltage control function from the channel doping process and relocates it to the gate metal layer. This separation allows the channel to remain undoped and high-mobility while the gate metal composition is adjusted to achieve the desired threshold voltage, effectively taking the harmful doping step out of the device structure
2Adaptability or versatility
If different threshold voltages are achieved through channel doping in scaled devices, then device functionality is enabled, but impurity scattering increases and mobility is reduced
Solution Approach 1:
The patent applies local quality by making the gate metal composition device-specific rather than uniform across all devices. Each device or device type (e.g., nFET, pFET) can have a locally optimized gate metal layer with the appropriate work function for its required threshold voltage, while the channel region maintains uniform high quality without scattering impurities
Solution Approach 2:
The patent employs composite gate stack structures combining multiple metal layers (e.g., titanium nitride barrier layer plus tungsten or cobalt work function metals) to achieve precise threshold voltage control. This composite approach allows fine-tuning of work function while maintaining good interface quality and avoiding channel doping
3Productivity
If optical lithography is used for device scaling, then manufacturing capability is improved, but minimum dimensions are limited by wavelength
Solution Approach 1:
The patent replaces the mechanical/optical lithography system with a self-aligned deposition and etching process for forming the gate metal layers. The gate metal pattern is defined by direct deposition on patterned substrates followed by selective removal, eliminating the diffraction-limited optical lithography step and enabling smaller feature sizes without requiring shorter wavelength light sources
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with distinct threshold voltages on a single substrate, improving device performance by avoiding the mobility degradation caused by channel doping, thus achieving high performance chips without the limitations of traditional threshold voltage tuning methods.
Implementation Method 1
a first metal layer is deposited on the first channel region, the second channel region, the third channel region, and the fourth channel region
Implementation Method 2
a work function metal is deposited on the first channel region, the second channel region, the third channel region, and the fourth channel region
Data Source
AI summary
A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.