High-Voltage Metal Gate CMP with Blocking Dielectric Against Dishing
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Solution Overview
Problem
The manufacturing of high-voltage metal gate devices faces issues with dishing during the CMP process, leading to reduced gate height and affecting the electrical properties of the device due to exposure of the gate dielectric layer.
Innovation Solution
A method involving the deposition of a blocking dielectric layer followed by selective etching and CMP processes to maintain the gate metal height and protect the gate dielectric layer, including steps like photolithography, etching, and CMP to control the gate metal thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a large gate size is used for high-voltage devices, then the device can undertake high-voltage operation, but CMP dishing will be caused resulting in gate height decline or loss
Solution Approach 1:
The patent segments the gate structure by introducing dummy poly gates at both ends of the high-voltage gate, separating the large gate area into multiple functional regions. This segmentation allows the CMP process to be controlled differently in different regions, preventing dishing in the main gate area while maintaining the required large gate size for high-voltage operation.
Solution Approach 2:
The patent performs preliminary actions by forming dummy poly gates and filling isolation dielectric before the main gate metal deposition and CMP process. This preliminary structuring creates a controlled topography that prevents dishing during the subsequent CMP process, ensuring gate height is maintained throughout the manufacturing sequence.
2Manufacturing precision
If a trench is added in the dummy polycrystalline to prevent CMP dishing, then dishing is avoided, but the gate dielectric layer is exposed and affected by ion implantation and etching
Solution Approach 1:
The patent introduces an intermediary protective layer (isolation dielectric) that fills the space between dummy poly gates and covers the gate dielectric layer. This intermediary layer prevents direct exposure of the gate dielectric to harmful processes like ion implantation and etching, while still allowing the CMP process to control gate metal thickness uniformly without dishing.
3Manufacturing precision
If the gate metal is deposited thick to maintain height, then gate height is maintained, but CMP dishing increases
Solution Approach 1:
The patent applies local quality by creating different structural conditions in different regions of the gate area. The dummy poly gates and isolation dielectric create localized variations in the CMP process, ensuring that the main gate metal area maintains uniform thickness and height without dishing, while other regions serve different functional purposes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents CMP dishing and maintains the electrical integrity of the high-voltage device by ensuring the gate metal height and protecting the gate dielectric layer from ion implantation and etching effects.
Implementation Method 1
Metal Chemical-Mechanical Polishing (CMP) process is inevitably used in the metal gate process
Implementation Method 2
A gate metal 5 is deposited on a wafer
Data Source
AI summary
The present application discloses a method for manufacturing a high-voltage metal gate device. After the deposition of a gate metal through a normal process, in CMP processes performed to the gate metal, firstly a first CMP process is performed to thin the gate metal to a certain thickness in advance, then a blocking dielectric layer is deposited, a large-area high-voltage gate region is opened through photolithography, and the blocking dielectric layer other than the blocking dielectric layer in the large-area high-voltage gate region is removed through etching. In a second CMP process performed to the gate metal, due to the blocking dielectric layer on the surface of the large-area gate metal in the high-voltage gate region, the polishing speed is slow, and CMP dishing will not be caused.