Metal Gate CMP Dishing Prevention via Etch Stop Layer
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Solution Overview
Problem
The increasing integration levels and reduced device features in semiconductor manufacturing, particularly in nanometer technology process nodes, lead to challenges such as dishing during the chemical mechanical planarizing (CMP) process, complicating the manufacturing process and affecting device performance.
Innovation Solution
A method for manufacturing a semiconductor device involving the formation of a metal gate structure with a dielectric layer, sidewall spacer, and etch stop layer, where the CMP process is optimized by planarizing the dielectric layer and recessing the etch stop layer to prevent dishing, allowing for precise control of the metal gate's position and reducing manufacturing complexities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to polish the surface, then surface planarity is improved, but dishing is induced on the surface
Solution Approach 1:
The polishing process is divided into two separate CMP steps: a first CMP process that polishes the initial surface, and a second CMP process that polishes after metal layer deposition. This segmentation allows each step to be optimized independently, preventing dishing from accumulating in a single prolonged polishing operation.
Solution Approach 2:
A metal layer is deposited on the semiconductor layer before the second CMP process. This preliminary metal layer acts as a protective cushion during polishing, preventing direct contact between the polishing pad and the underlying semiconductor structures, thereby avoiding dishing while still achieving the required surface planarity.
2Productivity
If integration levels are increased and device features are reduced, then device density is improved, but fabrication issues and manufacturing complexity increase
Solution Approach 1:
The manufacturing process is segmented into distinct stages with intermediate planarization steps. By dividing the fabrication process into manageable segments with planarity control at each stage, the overall complexity is reduced and each step can be optimized independently for nanometer-scale precision.
Solution Approach 2:
The process parameters are changed between the two CMP steps, including polishing pad conditions, slurry composition, and applied pressure. These parameter changes allow optimization for different stages of fabrication, enabling high device density while managing manufacturing complexity through controlled parameter adjustments.
3Manufacturing precision
If CMP process is used for planarization, then surface flatness is improved, but the manufacturing process becomes complicated
Solution Approach 1:
The metal layer deposition and planarization processes are merged into an integrated sequence where the metal layer serves dual purposes: as a functional component and as a protective layer during subsequent polishing. This merging reduces the need for additional separate protective layers and simplifies the overall manufacturing process.
Solution Approach 2:
The metal layer is given multiple functions: it serves as an electrical conductor, a structural element, and a protective cushion during CMP. This multi-functionality reduces the need for additional dedicated protective layers, thereby simplifying the manufacturing process while maintaining surface flatness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the manufacturing process by minimizing dishing and improving the precision and performance of semiconductor devices, enabling higher device density and performance while maintaining lower costs.
Implementation Method 1
In a fabrication process, a chemical mechanical planarizing (CMP) is used to polish a surface of a semiconductive structure
Data Source
AI summary
Some embodiments of the present disclosure provide a semiconductor device including a semiconductive substrate, a metal gate including a metallic layer proximal to the semiconductive substrate. A dielectric layer surrounds the metal gate. The dielectric layer includes a first surface facing the semiconductive substrate and a second surface opposite to the first surface. A sidewall spacer surrounds the metallic layer with a greater longitudinal height. The sidewall spacer is disposed between the metallic layer and the dielectric layer. An etch stop layer over the metal gate comprises a surface substantially coplanar with the second surface of the dielectric layer. The etch stop layer has a higher resistance to etchant than the dielectric layer. A portion of the etch stop layer is over the sidewall spacer.