Metal Gate Stack With Cobalt Layer for Low-Resistivity Transistors

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

MOS devices with polysilicon gate electrodes suffer from carrier depletion effects, leading to increased effective gate dielectric thickness and difficulty in creating an inversion layer, while tungsten nucleation layers in metal gates have high resistivity, impacting transistor performance, especially at small scales.

Innovation Solution

Forming metal gates with layers including a tungsten nucleation layer and a cobalt or metal silicide layer to improve adhesion and reduce resistivity, using deposition methods like CVD and CMP to achieve low resistivity and good adhesion to underlying layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a tungsten nucleation layer is formed to improve adhesion, then adhesion to underlying layers is improved, but resistivity increases significantly

Engineering Contradiction:
ImproveadhesionVSAvoidresistivity
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The metal gate is divided into multiple functional layers: a tungsten nucleation layer for adhesion, a cobalt or metal silicide layer for low resistivity, and an overlying tungsten layer. This segmentation allows each layer to optimize its specific function without compromising the others.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses a composite metal gate structure combining tungsten, cobalt, and metal silicide materials. Each material contributes its superior properties: tungsten for adhesion and structural integrity, cobalt/metal silicide for low resistivity, creating a composite system that achieves both good adhesion and low resistivity simultaneously.

Inventive Principle:
Principle #40Composite materials

2Productivity

If metal gates are scaled down to small dimensions, then device integration is improved, but the impact of nucleation layer resistivity on transistor performance increases

Engineering Contradiction:
Improvedevice integrationVSAvoidtransistor performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies different material properties to different regions of the metal gate structure. The nucleation layer provides local adhesion quality at the interface, while the cobalt/metal silicide layer provides local low-resistivity quality in the gate region, ensuring optimal performance at scaled dimensions.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If polysilicon gate electrodes are used, then work function adjustment is achieved, but carrier depletion effect occurs increasing effective gate dielectric thickness

Engineering Contradiction:
Improvework function adjustmentVSAvoidinversion layer creation
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent changes the fundamental parameter of gate material from polysilicon to metal (tungsten-cobalt/metal silicide stack). This parameter change eliminates the carrier depletion effect inherent in polysilicon while maintaining work function adjustability through material selection and doping control, thereby improving inversion layer creation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of cobalt and metal silicide layers in metal gates reduces resistivity and enhances adhesion, improving transistor performance by minimizing carrier depletion and maintaining low resistivity even at small dimensions.

Implementation Method 1

using deposition methods like CVD

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

using deposition methods like CVD

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

The tungsten nucleation layer has improved adhesion to its underlying layer

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS20250300016A1Metal gates of transistors having reduced resistivity
Publication Date: 2025.09.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250300016A1 patent drawing
  • US20250300016A1 patent drawing
  • US20250300016A1 patent drawing

AI summary

A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.