Metal Gate Contact Formation With Self-Aligned Conductive Layer

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Solution Overview

Problem

The integration of multiple work-function metal layers in metal gate structures leads to high-resistance interfaces with contact features, complicating the formation of low-resistance contacts in semiconductor devices, particularly as feature sizes decrease, making it difficult to control electrical properties at these interfaces.

Innovation Solution

A method involving the formation of a conductive layer on top of the metal gate structure using alternating deposition of gaseous precursors, followed by surface treatment with plasma to remove high-resistance materials, which promotes bonding and reduces contact resistance by forming a self-aligned conductive layer that can extend over the gate dielectric and capping layers, thereby improving contact feature integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple work-function metal layers are integrated in metal gate structures, then device performance is improved, but contact resistance at the interface with contact features increases

Engineering Contradiction:
Improvedevice performanceVSAvoidcontact resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A conductive layer is introduced as an intermediary between the metal gate structure and contact features. This conductive layer is formed by alternating deposition of gaseous precursors and plasma treatment, creating a self-aligned structure that reduces contact resistance while maintaining device performance benefits from multiple work-function metal layers

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If feature size is decreased to increase functional density, then production efficiency is improved, but control of electrical properties at contact interfaces becomes difficult

Engineering Contradiction:
Improveproduction efficiencyVSAvoidcontrol of electrical properties
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The conductive layer formation process is self-aligned, where the alternating deposition of gaseous precursors and plasma treatment automatically positions the conductive material at the contact interface without requiring additional alignment steps. This self-service mechanism maintains manufacturing precision despite reduced feature sizes

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The electrical properties at the contact interface are controlled by adjusting deposition parameters and plasma treatment conditions during conductive layer formation. These parameter changes enable precise control of contact resistance and other electrical properties even as feature sizes decrease

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces contact resistance at the interface between the metal gate and contact features, enhancing the overall performance of semiconductor devices by improving bonding and alignment, even in the presence of misalignment during fabrication.

Implementation Method 1

selectively depositing a conductive layer by a cyclic deposition technique using more than one gaseous species over a top surface of the gate electrode

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

surface treatment with plasma to remove high-resistance materials

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentUS11901426B2Forming metal contacts on metal gates
Publication Date: 2024.02.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11901426B2 patent drawing
  • US11901426B2 patent drawing
  • US11901426B2 patent drawing

AI summary

A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.