Metal Gate Contact Plug Formation via Multi-Layer Etching Masks
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with metal gate electrodes face challenges in efficiently forming contact plugs due to the complexity of etching masks and processes involved.
Innovation Solution
A method is developed that involves sequentially forming first and second etching masks on a metal gate structure, with a first insulating interlayer covering the sidewall, and removing portions to expose the substrate surface, forming a metal silicide pattern, and then creating a plug to fill the opening, using silicon nitride and spin-on-hard-mask layers for precise alignment and formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing methods are used to form contact plugs in semiconductor devices with metal gate electrodes, then the contact plugs can be formed, but the process complexity increases due to the complexity of etching masks and processes involved
Solution Approach 1:
The patent divides the etching mask into multiple layers (first etching mask layer, second etching mask layer, third etching mask layer) with each layer serving specific functions. The first layer defines the contact hole pattern, the second layer provides alignment reference with the metal gate electrode, and the third layer protects the contact hole bottom during silicidation. This segmentation allows precise control of contact plug formation while simplifying the overall process by assigning specific functions to each mask layer.
Solution Approach 2:
The patent forms the second etching mask layer on the first etching mask layer before etching the contact holes, establishing a reference structure that aligns with the metal gate electrode. This preliminary action ensures precise alignment between the contact holes and the gate electrode, improving manufacturing precision while avoiding complex alignment procedures during the etching process.
2Manufacturing precision
If existing methods are used to form contact plugs, then the contact plugs can be formed, but the process time increases due to multiple sequential steps
Solution Approach 1:
The patent combines the alignment reference function and the contact hole definition function into a multi-layer mask structure that is formed sequentially but functions as an integrated system. The first, second, and third etching mask layers are formed in sequence, but they work together to achieve precise alignment in a single contact hole formation process, reducing the need for separate alignment steps and thereby reducing overall process time.
Solution Approach 2:
The second etching mask layer is formed in advance on the first etching mask layer to establish the alignment reference before the actual contact hole etching begins. This preliminary formation of the reference structure eliminates the need for complex real-time alignment procedures during etching, thus reducing process time while maintaining high alignment precision.
3Ease of manufacture
If a single etching mask is used, then the process is simpler, but the alignment precision between contact holes and metal gate electrode decreases
Solution Approach 1:
The patent segments the mask structure into multiple functional layers: the first etching mask layer for contact hole pattern definition, the second etching mask layer for alignment reference, and the third etching mask layer for protection. This segmentation maintains ease of manufacture by using standard deposition and etching processes for each layer, while achieving high alignment precision through the collaborative function of all layers.
Solution Approach 2:
The second etching mask layer acts as an intermediary between the first etching mask layer (contact hole pattern) and the metal gate electrode. It provides a reference structure that mediates the alignment relationship, ensuring precise positioning of contact holes relative to the gate electrode without requiring direct complex interactions between the other components.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.