Metal Gate Contact Undercut for Reduced Resistance

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Solution Overview

Problem

The challenge in semiconductor device fabrication lies in the shrinking size of gate structures in MOSFET devices and the integration of high-k dielectric materials with metal gates, requiring improved methods for trench formation and metal gate replacement to enhance contact efficiency and reduce power consumption.

Innovation Solution

The method involves forming a substrate with a polysilicon gate structure, followed by doping and replacing it with a metal gate, and using a combination of dry and wet etch processes to create undercuts and fill trenches with conductive materials, such as tungsten, to increase contact area and reduce contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If a standard anisotropic etch process is used to create a trench in the dielectric, then the trench can be formed with good vertical profile, but the contact area with the metal gate structure is limited

Engineering Contradiction:
Improvecontact areaVSAvoidtrench profile control
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent transitions from a purely vertical trench etch to a two-stage process that creates both vertical walls and lateral undercuts. The first anisotropic etch establishes the vertical trench profile, while the second isotropic etch adds lateral dimensions by forming undercuts beneath the metal gate structure. This dimensional expansion significantly increases the contact surface area between the conductive material and metal gate without compromising the vertical alignment established in the first stage.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the gate structure size is shrunk to increase density, then device density and power reduction are achieved, but contact resistance increases due to reduced contact area

Engineering Contradiction:
Improvedevice densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by creating region-specific etching characteristics. The anisotropic etch provides precise vertical walls in the upper dielectric region, while the isotropic etch creates lateral undercuts in the lower dielectric region beneath the metal gate. This localized differentiation of etching behavior allows the contact structure to expand laterally at the bottom while maintaining vertical precision at the top, thereby increasing contact area and reducing contact resistance even in scaled devices.

Inventive Principle:
Principle #3Local quality

3Area of moving object

If only a single anisotropic etch process is used, then the process is simple and fast, but the contact area with metal gate structure is insufficient

Engineering Contradiction:
Improvecontact areaVSAvoidetch process complexity
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The etch process is segmented into two distinct stages with different characteristics. The first stage uses an anisotropic etch to create the initial vertical trench with good profile control. The second stage uses an isotropic etch to form lateral undercuts that expand the contact area. By dividing the etching operation into these two specialized segments, each optimized for its specific function, the process achieves superior contact area without requiring complete process redesign.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in reduced contact resistance and improved surface contact between gate contacts and metal gate stacks, enhancing the performance and density of integrated circuit devices.

Implementation Method 1

a wet etch process forms an undercut near the top surface of the metal gate structure

Methodology Applied
Scientific EffectWet etching:

Implementation Method 2

a dry etch process forms a trench in the ILD to a top surface of the metal gate structure

Methodology Applied
Scientific EffectDry etching:

Data Source

PatentUS8853753B2Contact for high-k metal gate device
Publication Date: 2014.10.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8853753B2 patent drawing
  • US8853753B2 patent drawing
  • US8853753B2 patent drawing

AI summary

An integrated circuit includes a semiconductor substrate including a source region and a drain region and a gate dielectric over the semiconductor substrate. A metal gate structure is over the semiconductor substrate and the gate dielectric and between the source and drain regions. The integrated circuit further includes an interlayer dielectric (ILD) over the semiconductor substrate. First and second contacts extend through the ILD and adjacent the source and drain regions, respectively, and a third contact extends through the ILD and adjacent a top surface of the metal gate structure. The third contact further extends into an undercut region of the metal gate structure.