Metal Gate Cut Plug Alignment for Tighter Nanowire Transistor Spacing
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is exacerbated by the trade-off between critical dimension and spacing constraints in lithographic processes during fabrication.
Innovation Solution
The implementation of a metal gate cut process subsequent to gate dielectric and work function metal deposition, allowing for a 'plug-last' approach that ensures seamless work function metal deposition and reduces space constraints, thereby improving registration and alignment in integrated circuit structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional processes are used to fabricate multi-gate transistors on bulk silicon substrates, then cost is reduced and fabrication process complexity is simplified, but device dimensions cannot be effectively scaled below 10 nanometer node while maintaining mobility improvement and short channel control
Solution Approach 1:
The transistor structure is segmented into multiple gates wrapping around the channel (tri-gate or gate-all-around configuration), enabling effective channel control at sub-10nm dimensions while maintaining compatibility with bulk silicon substrate fabrication processes. This segmentation allows the gate to control the channel from multiple directions, improving short channel control without requiring complete process redesign.
Solution Approach 2:
The gate structure transitions from a planar two-dimensional configuration to a three-dimensional multi-gate structure that wraps around the channel. This dimensional change enables effective electrostatic control of the channel at sub-10nm node while maintaining compatibility with conventional bulk silicon fabrication processes, resolving the contradiction between manufacturing simplicity and scaling precision.
2Area of moving object
If device dimensions are scaled down to increase functional unit density, then capacity is increased, but the trade-off between critical dimension and spacing constraints in lithographic processes becomes overwhelming
Solution Approach 1:
By transitioning to multi-gate structures with vertical or wrapped gate configurations, the patent exploits the third dimension to increase functional density without proportionally reducing lateral spacing requirements. This allows higher device density while maintaining lithographic processability, as the critical lithographic dimensions are less constrained compared to planar devices.
Solution Approach 2:
The patent changes key geometric parameters of the transistor structure, including channel orientation, gate wrapping angle, and fin dimensions, to optimize the balance between device density and lithographic spacing constraints. These parameter changes enable effective scaling while maintaining manufacturing feasibility.
3Manufacturing precision
If a metal gate cut process is performed subsequent to gate dielectric and work function metal deposition, then seamless work function metal deposition is achieved and space constraints are reduced, but process complexity increases
Solution Approach 1:
The gate dielectric and work function metal are deposited in advance before the metal gate cut operation. This preliminary action ensures seamless deposition and proper alignment, as subsequent steps reference these pre-formed structures. The earlier deposition establishes precise registration boundaries that guide later processing steps.
Solution Approach 2:
Instead of performing the metal gate cut before depositing the gate dielectric and work function metal (conventional sequence), the patent inverts the sequence by cutting the metal gate after these layers are already in place. This inversion enables seamless deposition and improved alignment while the cut is performed as a finishing operation.
Data Source
AI summary
Integrated circuit structures having a metal gate cut plug and an alignment structure are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate electrode is over the vertical stack of horizontal nanowires or the fin. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and past the conductive trench contact. A semiconductor structure is adjacent to a side of the dielectric cut plug structure opposite the gate electrode, the dielectric sidewall spacer, and the conductive trench contact. A dielectric structure covers a top and sides of the semiconductor structure, the dielectric structure in contact with the side of the dielectric cut plug structure.