Metal Gate Cut CMP for Coplanar Contact Isolation
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Solution Overview
Problem
As integrated circuits shrink in size, forming gate cuts that are accurately coplanar with source and drain contacts becomes challenging due to the increased density of device packing, leading to difficulties in controlling the height of metal gate cuts and isolating adjacent transistors effectively.
Innovation Solution
The technique involves forming source and drain contacts before gate cuts, using chemical mechanical polishing (CMP) to polish a dielectric material until its top surface is substantially coplanar with the source and drain contacts, thereby controlling the height of the gate cut and ensuring electrical isolation between gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated circuits are scaled down in size to increase device density, then productivity and integration density are improved, but manufacturing precision deteriorates due to difficulties in forming gate cuts coplanar with source and drain contacts
Solution Approach 1:
Source and drain contacts are formed prior to gate cut formation, establishing reference surfaces in advance. This preliminary action allows the gate cut depth to be controlled relative to the already-formed contact tops, ensuring coplanarity despite circuit scaling. The contacts serve as pre-established references that guide subsequent gate cut fabrication.
2Productivity
If device spacing is reduced to increase integration density, then productivity is improved, but manufacturing precision deteriorates due to challenges in isolating adjacent transistors
Solution Approach 1:
Gate cuts are formed after source and drain contacts are established, using the contacts as reference structures. This sequencing ensures that even when device spacing is reduced, the gate cuts can be precisely positioned relative to the contacts, maintaining proper transistor isolation. The preliminary formation of contacts provides fixed reference points that enable accurate gate cut placement in densely packed devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for precise control of gate cut height, enhancing the ability to isolate gate structures and maintain the integrity of transistor spacing in densely packed integrated circuits, improving fabrication accuracy and device performance.
Implementation Method 1
chemical mechanical polishing (CMP) to polish a dielectric material until its top surface is substantially coplanar with the source and drain contacts
Data Source
AI summary
Techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source or drain contacts and with a top surface that is substantially coplanar with a top surface of the source or drain contacts. An example semiconductor device includes a gate structure around or otherwise on a semiconductor region and a dielectric layer present on a top surface of the gate structure. Conductive contacts are formed over source and drain regions along a source/drain contact recess or trench. The gate structure may be interrupted with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material. A top surface of the gate cut may be polished until it is substantially coplanar with a top surface of the dielectric layer over the gate structure and a top surface of the source or drain contacts.