Metal Gate Cut Depth Control Using Isolation Material
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Solution Overview
Problem
As semiconductor technology advances and integrated circuit dimensions are scaled down, the critical dimension requirements for the cut operation on semiconductor wafers become more stringent, leading to potential damage of semiconductor elements during the etching process.
Innovation Solution
A method is introduced where a portion of the inter-layer dielectric layer is replaced with an isolation material before the metal gate cut operation, creating an isolation portion adjacent to the metal gate structure. This isolation portion has a lower etching selectivity than the metal gate structure, preventing excessive etching and protecting the source/drain devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a cut operation is performed on the semiconductor wafer to package and produce semiconductor chips, then the semiconductor chips can be produced, but the semiconductor elements are easily damaged by an etchant during the cut operation
Solution Approach 1:
A sacrificial material layer is introduced as an intermediary between the etchant and the semiconductor elements. This sacrificial layer has high etching selectivity, meaning it etches much faster than the semiconductor elements. The sacrificial material absorbs the etchant's harmful effects, protecting the underlying semiconductor elements from damage while still allowing the cut operation to proceed effectively
Solution Approach 2:
The sacrificial material layer is deposited in advance before the cut operation. This preliminary action prepares a protective barrier that will be consumed during etching, preventing direct contact between the etchant and the semiconductor elements. The sacrificial layer is strategically positioned to provide protection exactly where needed during the subsequent cut operation
2Manufacturing precision
If the critical dimension requirements become more stringent as technology node sizes decrease, then the precision of integrated circuit dimensions is improved, but the semiconductor elements are more susceptible to damage during the cut operation
Solution Approach 1:
The sacrificial material layer serves as a mediator that decouples the precision requirements from the damage risk. By providing a dedicated sacrificial layer with controlled thickness and high etching selectivity, the process allows for precise dimension control while the sacrificial material absorbs the mechanical and chemical stresses of the cut operation, protecting the precisely-formed semiconductor elements
Solution Approach 2:
The etching selectivity parameter is optimized to create a large difference in etching rates between the sacrificial material and the semiconductor elements. This parameter change ensures that the etchant removes the sacrificial material rapidly while leaving the semiconductor elements virtually untouched, even under stringent critical dimension requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents damage to source/drain devices during the metal gate cut operation while meeting the stringent critical dimension requirements of integrated circuit dimensions, ensuring precise cutting without compromising the semiconductor elements.
Implementation Method 1
An etchant of the metal gate cut operation has a lower etching selectivity with respect to the isolation portion than to the metal gate structure
Data Source
AI summary
A method incudes forming first and second semiconductor fins upwardly extending from a substrate; forming a gate strip extending across the first and second semiconductor fins; growing first source/drain regions on the first semiconductor fin and at opposite sides of the gate strip, second source/drain regions on the second semiconductor fin and at opposite sides of the gate strip; depositing a dielectric layer over the first and second source/drain regions; forming an isolation material in the dielectric layer and between one of the first source/drain regions and one of the second source/drain regions; performing an etching process on the isolation material and the gate strip to form an opening, the opening breaking the grid strip and recessing the isolation material; forming a separation material in the opening.