Metal Gate Cut Etch Stop Layer for Uniform Trench Height

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Solution Overview

Problem

The challenge in integrated circuit fabrication lies in forming gate cuts between transistor devices without extending trenches deep into the substrate, which complicates backside polishing and leads to variations in gate cut heights, affecting the uniformity and precision of device structures.

Innovation Solution

Incorporating an etch stop layer composed of dielectric material between sub-fins, which stops or dampens the etch process, ensuring that gate cut trenches do not reach the substrate and maintaining uniformity in gate cut heights, thereby facilitating backside polishing and reducing loading effects during high aspect ratio etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If gate cut trenches are formed without an etch stop layer, then the etching process can proceed freely, but the gate cut heights vary greatly and trenches may extend too deep into the substrate

Engineering Contradiction:
Improvegate cut height uniformityVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

An etch stop layer comprising silicon nitride is introduced between the metal gate electrode and the underlying dielectric material. This intermediary layer acts as a barrier that stops or dampens the etch process, preventing trenches from extending too deep into the substrate and ensuring uniform gate cut heights across different devices.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If gate cut trenches extend deep into the substrate, then complete isolation between adjacent gates is achieved, but backside polishing becomes difficult and variations in gate cut heights increase

Engineering Contradiction:
Improvegate isolation effectivenessVSAvoidbackside polishing ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The etch stop layer is deposited beforehand during the gate formation process, before the metal gate electrode is fully formed. This preliminary action ensures that when subsequent etching occurs, the trench depth is automatically limited by the etch stop layer, preventing excessive penetration into the substrate and facilitating later backside polishing operations.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If no etch stop layer is used, then the fabrication process is simpler, but loading effects during high aspect ratio etching increase and uniformity is reduced

Engineering Contradiction:
Improvefabrication process efficiencyVSAvoidgate cut height consistency
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etch stop layer changes the etching parameters by introducing a material with different etch selectivity. The silicon nitride layer has lower etch rate compared to the metal gate electrode, which dampens the etch process and reduces loading effects. This parameter change ensures more consistent gate cut heights while maintaining overall process efficiency.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures uniform gate cut heights, prevents deep substrate penetration, and simplifies the backside polishing process, enhancing the precision and reliability of integrated circuit fabrication.

Implementation Method 1

The etch stop layer stops or dampens etch processes used to form trenches for the gate cuts

Methodology Applied
Scientific EffectEtch stop layer effect:

Data Source

PatentUS20240113106A1Etch stop layer for metal gate cut
Publication Date: 2024.04.04 INTEL CORP
  • US20240113106A1 patent drawing
  • US20240113106A1 patent drawing
  • US20240113106A1 patent drawing

AI summary

An integrated circuit includes laterally adjacent first and second devices. The first device includes (i) first source and drain regions, (ii) a first body including semiconductor material laterally extending between the first source and drain regions, (iii) a first sub-fin below the first body, and (iv) a first gate structure on the first body. The second device includes (i) second source and drain regions, (ii) a second body including semiconductor material laterally extending from the second source and drain regions, (iii) a second sub-fin below the second body, and (iv) a second gate structure on the second body. A second dielectric material is laterally between the first and second sub-fins. A third dielectric material is laterally between the first and second sub-fins, and above the second dielectric material. A gate cut including first dielectric material is laterally between the first and second gate structures, and above the third dielectric material.