Metal Gate Cut Profile for FinFET Isolation
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in achieving suitable isolation between cut metal gate segments in FinFET devices, leading to issues such as insufficient isolation and difficulties in filling the cut region with dielectric material, which can result in degraded device reliability and performance.
Innovation Solution
A metal gate cut process and related structure that provides a specific profile for the cut gate segment, allowing for improved isolation between the cut segments, involving a patterned hard mask layer and etching processes to create an opening with linear sidewalls and a tapered profile, enabling effective dielectric filling and enhanced electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal gate line cut process is used, then metal gate electrode can be formed, but isolation between cut segments is insufficient and device reliability degrades
Solution Approach 1:
The patent divides the gate cut region into multiple segments with distinct profiles. The cut profile is segmented into a first portion within the ILD layer and a second portion extending into the STI layer, with different width characteristics at each segment to achieve both complete filling and adequate isolation
Solution Approach 2:
The patent applies different geometric characteristics to different portions of the cut profile. The first portion has a first width while the second portion has a second width greater than the first width, creating local quality variations that enable both complete dielectric filling and sufficient electrical isolation between gate segments
2Manufacturing precision
If conventional cut profile is used, then fabrication is simpler, but dielectric material filling is difficult and isolation is insufficient
Solution Approach 1:
The patent performs preliminary shaping of the cut profile before dielectric filling. By pre-forming the tapered profile with the opening at the top and narrower base at the bottom, the structure is prepared in advance to receive dielectric material, ensuring complete filling while maintaining the complexity of the profile structure
Solution Approach 2:
The patent extends the cut profile into the vertical dimension by forming a tapered structure that varies in width from top to bottom. This dimensional variation creates a self-filling geometry where the narrowing profile toward the bottom ensures complete dielectric material deposition and adequate isolation
3Reliability
If metal gate electrode is introduced, then polysilicon depletion effect is avoided, but line cut process causes ILD loss and residue issues
Solution Approach 1:
The patent introduces a patterned hard mask layer as an intermediary between the metal gate electrode and the ILD layer during the cut process. This hard mask protects the ILD from excessive etching and material loss while allowing precise definition of the gate cut segments, preventing both ILD loss and metal residue issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution improves the isolation between cut metal gate segments, mitigating current leakage and enhancing transistor performance by ensuring complete filling of the cut region with dielectric material, thereby improving the reliability and efficiency of FinFET devices.
Implementation Method 1
The gate structure and the dielectric layer are etched to form an opening in the gate structure
Implementation Method 2
perform a first process to deposit a silicon layer
Data Source
AI summary
A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.