High-Aspect-Ratio Metal Gate Cuts for Dense Transistor Isolation
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Solution Overview
Problem
As integrated circuits shrink in size, forming high aspect ratio gate cuts in semiconductor devices becomes challenging due to limitations in current fabrication technologies, leading to issues with device isolation and increased manufacturing costs.
Innovation Solution
A plasma etching process is employed to create gate cuts with a high height-to-width aspect ratio of 5:1 or greater, using a series of finely-tuned passivation and etching processes to maintain verticality and reduce taper, thereby improving selectivity and material compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used to form gate cuts, then manufacturing simplicity is maintained, but the aspect ratio of gate cuts is insufficient and device isolation is compromised
Solution Approach 1:
The gate cut formation process is divided into multiple discrete steps: forming opening through mask layer, depositing liner material, depositing passivation layer, etching through passivation layer, etching gate structure, and repeating cycles. This segmentation allows each step to be optimized independently to achieve the high aspect ratio while maintaining process control
Solution Approach 2:
Liner material and passivation layer are deposited beforehand before etching the gate structure. This preliminary action protects the gate structure during etching and enables the formation of vertical sidewalls with minimal taper, achieving the required aspect ratio
2Productivity
If gate cut width is reduced to increase device density, then device spacing is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
Liner material and passivation layer act as intermediary protective layers during the etching process. These layers enable precise control of the gate cut width by protecting sidewalls from etching, maintaining vertical profiles even at reduced widths for high device density
Solution Approach 2:
The process uses periodic cycles of depositing passivation layer, etching through it, and removing portions. This periodic action allows incremental formation of the gate cut with precise width control, maintaining manufacturing precision at smaller dimensions
3Manufacturing precision
If repeated passivation and etching cycles are performed to achieve high aspect ratio, then gate cut verticality is improved, but processing time increases
Solution Approach 1:
The process deposits passivation layer in multiple thin cycles rather than one thick layer, and etches through only the necessary portion each cycle. This partial action approach achieves vertical sidewalls with minimal taper while reducing total processing time compared to single-step excessive etching
4Reliability
If gate cut aspect ratio is increased to improve device isolation, then device spacing is reduced, but fabrication difficulty increases
Solution Approach 1:
Liner material and passivation layer serve as intermediary protective structures that enable the formation of high aspect ratio gate cuts with vertical sidewalls. These intermediaries protect the gate structure during etching, making the fabrication of high aspect ratio cuts feasible and reliable for improved device isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process achieves densely integrated devices with reduced manufacturing costs by 25-35% and maintains vertical sidewalls, enhancing the operational variability and material compatibility of gate cuts.
Implementation Method 1
A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio
Data Source
AI summary
Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.