Metal Gate Opening Structure for Dense Fill and Short Isolation
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Solution Overview
Problem
The existing 'gate-last' process for forming metal gates in semiconductor fabrication faces challenges such as poor material filling due to high aspect ratios of gate openings, leading to loose gate layer structures and increased resistance, as well as the risk of short circuits from conductive plugs contacting gate layers.
Innovation Solution
The semiconductor structure and method involve forming gate openings with specific projections and regions, where the second projection area is larger than the first, allowing easier material filling and dense gate layer formation, and incorporating a barrier layer in the third region to prevent short circuits by limiting conductive plug placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate opening has a high aspect ratio in the existing gate-last process, then the gate opening can accommodate the required gate structure, but the material filling becomes poor leading to loose gate layer structure and increased resistance
Solution Approach 1:
The gate opening is divided into two distinct regions: a first region with a smaller cross-sectional area and a second region with a larger cross-sectional area. This segmentation allows the first region to accommodate the gate electrode while the second region provides a wider opening for improved material filling and deposition, thereby achieving dense gate layer structure with lower resistance.
Solution Approach 2:
The patent introduces a dimensional variation in the gate opening structure by creating a two-region configuration where the second region extends laterally beyond the first region. This dimensional change provides a broader deposition area for gate materials, improving filling efficiency and reducing the aspect ratio effect without increasing the vertical depth of the gate opening.
2Productivity
If conductive plugs are placed in the dielectric layer, then electrical connections are established, but short circuits may occur when conductive plugs contact gate layers
Solution Approach 1:
The patent performs preliminary action by forming the second region with larger cross-sectional area before placing conductive plugs. This pre-configured wider region creates a natural separation zone that prevents conductive plugs from contacting the gate electrode in the first region, thereby eliminating short circuit risk while maintaining electrical connection functionality.
Solution Approach 2:
The second region acts as an intermediary structure between the gate electrode in the first region and the conductive plugs in the dielectric layer. This intermediate region provides physical separation and isolation, preventing direct contact between conductive plugs and gate layers while still allowing proper electrical connection formation.
Data Source
AI summary
A semiconductor structure and a method for forming semiconductor structure are provided. The semiconductor structure includes a substrate and a dielectric layer on the substrate, the dielectric layer containing gate openings. Each gate opening includes a first region and a second region on the first region. The first region has a first projection on the substrate, the second region has a second projection on the substrate. An area of the second projection is larger than an area of the first projection, and the first projection is located within the second projection. A gate layer is located in each first region and one corresponding second region.