Metal Gate Stack Layout for Dense FinFET and GAA Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues in achieving reliable transistor structures and maintaining production efficiency.
Innovation Solution
The process involves forming FinFET and gate all around (GAA) transistor structures using double-patterning or multi-patterning techniques, which allow for the creation of smaller pitches and more complex patterns, along with the use of sacrificial layers and epitaxial growth to form channel structures and source/drain regions, enabling precise control over transistor dimensions and materials to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming first and second trenches at different depths, selective epitaxial growth in specific regions, and staged doping processes. This segmentation allows complex device formation to be broken down into manageable steps that can be executed with existing fabrication tools while maintaining precision at reduced feature sizes
Solution Approach 2:
The patent introduces vertical dimensionality by forming trenches at different depths (first trench extending to first depth, second trench extending to second depth greater than first depth) and performing selective epitaxial growth in specific vertical zones. This multi-level vertical structure enables complex device functionality to be achieved without requiring proportionally more complex lateral patterning processes
2Productivity
If feature sizes are decreased to increase functional density, then chip area utilization is improved, but manufacturing reliability deteriorates
Solution Approach 1:
The patent applies different materials and processing conditions to specific local regions: semiconductor material is selectively grown only in the second trench region, doping is applied selectively to different zones, and the first and second trenches have different depths and fill conditions. This local differentiation ensures that each region of the device receives optimized treatment for its specific function, maintaining reliability even as overall feature sizes decrease
Solution Approach 2:
The patent forms a first trench and fills it with dielectric material before forming the second trench. This sequential approach provides structural support and isolation beforehand, cushioning against potential manufacturing variations and ensuring that subsequent processing steps have a stable foundation, thereby maintaining device reliability at smaller dimensions
3Productivity
If double-patterning or multi-patterning techniques are used to create smaller pitches, then transistor density is improved, but process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the first trench and filling it with dielectric material before forming the second trench. This preliminary structuring creates a template that guides subsequent patterning steps, allowing multi-patterning to be executed more systematically and reducing the overall complexity of achieving high transistor density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reliable formation of semiconductor devices with improved channel structures and source/drain regions, enhancing current flow and reducing parasitic capacitance, thus improving the operational speed and reliability of semiconductor devices.
Implementation Method 1
a first semiconductor layer and a second semiconductor layer are formed over the fin structure
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure, and the first gate stack has a first width. The semiconductor device structure further includes a second gate stack over the second channel structure. The second gate stack has a protruding portion extending away from the second channel structures. The protruding portion of the second gate stack has a second width, and half of the first width is greater than the second width.