Metal Gate Formation via Dummy Filling Material Segmentation
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Solution Overview
Problem
The integration of metal-oxide-semiconductor field-effect transistors (MOSFETs) faces challenges in scaling down due to issues with forming a metal gate (MG) stack, particularly in pairing work-function (WF) metals with fill metals during the etching process, which affects the complexity and efficiency of IC processing and manufacturing.
Innovation Solution
A method for fabricating semiconductor integrated circuits (ICs) that involves forming a gate stack with an interfacial layer, using a dummy-filling-material (DFM) to separate the WF metal stack formation from the fill metal process, and employing a replacement gate scheme to relax process constraints and improve etching selectivity, allowing for adjustable fill metal and WF metal stack heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If work-function (WF) metals and fill metals are paired together for metal gate (MG) formation, then the MG stack can be formed, but the process complexity increases due to the need to coordinate multiple metal layers and etching selectivity requirements
Solution Approach 1:
The patent segments the MG formation process into distinct phases: first forming the WF metal stack, then separately forming the fill metal layer. This segmentation allows each metal layer to be optimized independently, reducing the complexity of coordinating multiple metals simultaneously while maintaining formation reliability.
Solution Approach 2:
The WF metal stack is formed in advance before the fill metal is deposited. This preliminary action establishes the gate structure foundation first, allowing subsequent fill metal deposition to proceed independently without affecting the already-formed WF metal stack, thereby simplifying the overall process coordination.
2Reliability
If traditional metal gate formation processes are used, then the gate stack can be formed, but manufacturing efficiency decreases due to process constraints and the need for precise coordination of multiple steps
Solution Approach 1:
By dividing the gate stack formation into separate WF metal stack and fill metal deposition steps, the patent enables parallel processing and independent optimization of each step, thereby improving manufacturing efficiency without compromising the reliability of the final gate stack structure.
Solution Approach 2:
The patent introduces adjustable parameters including fill metal height and WF metal stack height, allowing process optimization for different device requirements. This flexibility improves manufacturing efficiency by enabling standardized processes to be adapted to various product specifications without retooling.
3Productivity
If fill metal and WF metal are formed simultaneously, then the process steps are reduced, but etching selectivity becomes difficult to control and process constraints increase
Solution Approach 1:
The patent separates WF metal stack formation and fill metal deposition into distinct process steps, allowing each step to be optimized for its specific requirements. The WF metal stack step can be optimized for adhesion and work function, while the fill metal step can be optimized for conductivity and planarity, thereby maintaining high etching selectivity without sacrificing process efficiency.
Data Source
AI summary
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a semiconductor substrate and forming a gate trench therein. The method also includes filling in the gate trench partially with a work-function (WF) metal stack, and filling in the remaining gate trench with a dummy-filling-material (DFM) over the WF metal stack. A sub-gate trench is formed by etching-back the WF metal stack in the gate trench, and is filled with an insulator cap to form an isolation region in the gate trench. The DFM is fully removed to from a MG-center trench (MGCT) in the gate trench, which is filled with a fill metal.