Replacement Metal Gate Dielectric Cap for Plasma Protection
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Solution Overview
Problem
As semiconductor technology advances, the small dimensions and tight spacing of transistors pose challenges in protecting replacement metal gates from damage during contact formation, particularly due to lithographic alignment errors and etch plasma exposure, which can lead to yield detractors and device damage.
Innovation Solution
A dielectric cap is formed on top of the replacement metal gate using a selective deposition process, employing a chelating mask to prevent material deposition on the gate surface while allowing deposition on the field oxide, providing self-aligned protection and minimizing exposure to etch plasma.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a replacement metal gate is used in a field effect transistor, then the transistor can operate at smaller dimensions with tighter spacing, but the metal gate becomes vulnerable to damage from lithographic alignment errors and etch plasma exposure during contact formation
Solution Approach 1:
A dielectric cap is introduced as an intermediary protective layer between the etch plasma and the replacement metal gate. This cap acts as a mediator that absorbs the harmful effects of plasma exposure and prevents direct contact with the gate structure, thereby protecting the gate while enabling continued scaling to smaller dimensions
2Ease of manufacture
If contact holes are formed during manufacturing, then electrical connections are established, but lithographic alignment errors can cause misaligned contact holes that damage the gate and spacer structures
Solution Approach 1:
The dielectric cap is formed beforehand on the replacement metal gate to provide a cushioning protective layer before contact hole formation. This pre-established protection absorbs misalignment errors during subsequent lithography and etching processes, preventing damage to the underlying gate and spacer structures even when contact holes are not perfectly aligned
3Productivity
If the transistor pitch is reduced below 100 nanometers, then device density increases, but the risk of plasma damage and alignment errors increases proportionally
Solution Approach 1:
The dielectric cap is formed in advance on the replacement metal gate before any contact formation or plasma exposure steps. This preliminary protective action ensures that when plasma etching is performed for contact hole formation, the gate is already protected, allowing safe processing at reduced pitches below 100 nanometers where alignment margins are minimal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dielectric cap effectively protects the replacement metal gates from misaligned contact holes and plasma damage, enhancing the yield and reliability of integrated circuits by preventing unintended contact with the gate and spacer structures, especially for transistors with gate lengths below 25 nanometers and pitches below 100 nanometers.
Implementation Method 1
a chelating mask chelated to the metal top surface and fill top surface of a replacement metal gate
Implementation Method 2
A dielectric cap is formed on top of the replacement metal gate using a selective deposition process
Data Source
AI summary
A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.