Metal Gate Stack Diffusion Barrier for High-k Dielectrics
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Solution Overview
Problem
In CMOS technology, unwanted diffusion of oxygen (O2) and hydroxide (OH−) atoms into high-k gate dielectric layers affects the threshold voltage and workfunction performance of FET devices, particularly in gate structures with lengths less than or equal to 20 nm, leading to decreased device performance and variability in threshold voltage between short-gate and long-gate devices.
Innovation Solution
A method involving the recessing of the gate dielectric layer prior to the deposition of a conductive barrier, which acts as a barrier to block diffusion paths for O2 and OH−, thereby reducing their migration to the gate dielectric layer, and the formation of a metal gate stack with a conductive barrier separating the capping layer from the recessed gate dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional gate stack configuration is used with the gate dielectric layer directly exposed, then the device structure is simple and easy to manufacture, but oxygen and hydroxide diffusion occurs from the capping layer to the gate dielectric layer, degrading device performance
Solution Approach 1:
The gate stack is segmented into distinct functional layers: the gate dielectric layer, a recessed region, and a conductive barrier layer. This segmentation isolates the gate dielectric from direct exposure to the capping layer, preventing harmful diffusion while maintaining structural integrity and device performance.
Solution Approach 2:
The conductive barrier layer acts as an intermediary between the capping layer and the gate dielectric layer. It physically blocks the diffusion path for oxygen and hydroxide atoms, preventing contamination of the gate dielectric while still allowing the gate structure to function properly.
2Reliability
If the gate dielectric layer is recessed and a conductive barrier is added, then diffusion of O2 and OH− is blocked, but the manufacturing process becomes more complex
Solution Approach 1:
The gate dielectric layer is recessed before the conductive barrier layer is deposited. This preliminary action creates a controlled geometry that facilitates subsequent barrier layer formation and ensures complete coverage, making the overall process more manageable despite the additional steps required.
Solution Approach 2:
The local thickness parameter of the gate dielectric layer is changed by creating a recessed region. This parameter modification allows the conductive barrier to be positioned optimally for blocking diffusion while maintaining compatibility with standard fabrication processes.
3Manufacturing precision
If no protective measure is taken, then the fabrication process is fast and simple, but threshold voltage variability increases between short-gate and long-gate devices
Solution Approach 1:
The protective structure is applied locally at the gate dielectric-capping layer interface where diffusion occurs, rather than uniformly across the entire device. This localized approach prevents threshold voltage variability without adding excessive process steps, maintaining productivity while improving precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces O2 and OH− diffusion, stabilizing the threshold voltage and workfunction, enhancing device performance, increasing product yield, and reliability while maintaining the traditional gate stack configuration.
Implementation Method 1
unwanted diffusion of oxygen (O2) and hydroxide (OH−) atoms into high-k gate dielectric layers
Data Source
AI summary
A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.