Metal Gate Stack Dipole Tuning for Scaled Threshold Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in continuously scaling down gate stacks for devices in different regions with a wide threshold voltage tuning range, as existing multiple gate field-effect transistors and processes are not entirely satisfactory.
Innovation Solution
A doping layer with dipole-inducing elements is formed on a gate dielectric layer, driven through by an annealing process to create dipoles at the interface, followed by removal of the doping layer, and a work function metal layer with an oxygen blocking layer is formed to control threshold voltages, preventing oxygen diffusion and maintaining dipole density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing multiple gate field-effect transistors and processes are used, then device functionality is achieved, but threshold voltage tuning range is limited and scaling down is difficult
Solution Approach 1:
The patent applies local quality by forming a doping layer with dipole-inducing elements (such as aluminum, titanium, zirconium, hafnium, magnesium, germanium, yttrium, lutetium, lanthanum, strontium, or combinations) at specific locations within the gate stack structure. This doping layer is positioned between the gate electrode and gate dielectric, creating localized dipole moments that enable precise threshold voltage tuning in different device regions without requiring complex process changes across the entire fabrication line.
Solution Approach 2:
The patent utilizes parameter changes by controlling the composition, thickness, and dipole moment of the doping layer to achieve a wide threshold voltage tuning range. By adjusting the concentration of dipole-inducing elements and the layer thickness (typically 1-10 nm), the effective work function of the gate can be tuned continuously, enabling threshold voltages from negative to positive values while maintaining a unified gate stack architecture that simplifies scaling.
2Reliability
If different threshold voltages are required for I/O and core functions, then device performance is optimized, but manufacturing process complexity increases
Solution Approach 1:
The patent implements universality by using a single, unified gate stack structure and fabrication process that can produce transistors with different threshold voltages for both I/O and core functions. The doping layer with dipole-inducing elements serves multiple functions: it enables threshold voltage tuning, maintains gate dielectric integrity, and works across different transistor types (nMOS and pMOS) without requiring separate processing lines, thereby optimizing device performance while simplifying manufacturing.
Solution Approach 2:
The patent applies preliminary action by forming the doping layer with dipole-inducing elements during the gate stack fabrication process itself, rather than requiring subsequent threshold voltage adjustment steps. This preliminary doping action establishes the desired threshold voltage characteristics before device assembly, enabling different threshold voltages for I/O and core transistors to be achieved through a single unified process flow.
3Productivity
If gate stacks are scaled down continuously, then production efficiency increases and costs decrease, but threshold voltage control becomes more difficult
Solution Approach 1:
The patent maintains threshold voltage control precision during scaling by using the doping layer with dipole-inducing elements, whose effect is dominated by interfacial dipole moments rather than absolute layer thickness. This allows the same doping layer composition and thickness to provide consistent threshold voltage tuning across different device scales, enabling continuous gate stack scaling while maintaining precise threshold voltage control through parameter optimization of the dipole layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for effective control of threshold voltages in transistors across different regions, enhancing the ability to tune and maintain threshold voltage ranges, thereby addressing the scaling challenges and improving manufacturing efficiency.
Implementation Method 1
an annealing process to drive the dipole-inducing element through the gate dielectric layer
Implementation Method 2
an oxygen blocking layer is formed on the work function metal layer. By forming the oxygen blocking layer, oxygen atoms from ambient environment are blocked from diffusing to where the dipole interfaces are formed
Data Source
AI summary
A semiconductor device includes an interface layer on a substrate, a gate dielectric layer on the interface layer, and a work function metal layer on the gate dielectric layer. An interface between the interface layer and the gate dielectric layer has a concentration of a dipole-inducing element. The semiconductor device also includes an oxygen blocking layer on the work function metal layer and a metal fill layer on the oxygen blocking layer.