Metal Gate Electrode Dishing Prevention via Dielectric Trench
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Solution Overview
Problem
In the 'gate last' process of CMOS fabrication, dishing in metal gate electrodes during chemical mechanical polishing (CMP) leads to device instability and failure, affecting the performance and yield of semiconductor devices like MOSCAPs and MOSFETs due to reduced gate heights and shifts in work function and capacitance-voltage characteristics.
Innovation Solution
A method is introduced where a dielectric feature is formed in the trench of the metal electrode, which is then planarized using CMP, preventing dishing and maintaining the desired gate height and work function, thereby stabilizing the device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal gate electrode is formed using gate last process, then device performance is improved with decreased feature sizes, but dishing is generated during CMP process leading to device instability and failure
Solution Approach 1:
A dummy gate structure is formed in advance before the actual metal gate electrode fabrication. This dummy gate serves as a sacrificial structure that maintains the desired gate height and flatness during subsequent CMP processes. The dummy gate is removed later and replaced with the final metal gate electrode, thereby preventing dishing from occurring in the actual gate electrode.
Solution Approach 2:
The dummy gate acts as an intermediary structure between the substrate and the final metal gate electrode. It absorbs the mechanical stress and dishing effects during CMP, protecting the actual gate electrode from deformation. This intermediary structure enables the use of CMP for planarization without compromising the integrity of the gate electrode.
2Shape
If CMP process is performed on metal gate electrode, then surface planarity is improved, but dishing occurs causing reduced gate heights and work function shifts
Solution Approach 1:
The dummy gate is formed with the desired height and planarity characteristics before any CMP processing. During CMP, the dummy gate is planarized instead of the actual metal gate electrode, preserving the gate height and preventing dishing. The dummy gate structure is designed to accommodate CMP-induced material removal without affecting the final gate dimensions.
Solution Approach 2:
The dummy gate is created as a copy or replica of the intended metal gate electrode structure. It replicates the critical dimensions and geometry needed for device operation. By processing the dummy gate instead of the actual electrode, the copying principle ensures that the final metal gate electrode retains the precise dimensions and shape required for optimal device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents dishing in the metal electrode during CMP processes, ensuring consistent gate heights and work function, thereby improving device stability and yield by maintaining desirable threshold voltage and depth of focus in semiconductor devices.
Implementation Method 1
dishing in a metal gate electrode is generated after a metal chemical mechanical polishing (CMP) process
Data Source
AI summary
The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.