Metal Gate Recess Structure for Compact Display Driver Integration
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Solution Overview
Problem
Current head-mounted displays for augmented reality (AR) and virtual reality (VR) applications face challenges due to the use of long wires or metal interconnections that consume space and complicate device mounting, particularly in larger scale products.
Innovation Solution
A semiconductor device design featuring a metal gate with a recess between the interlayer dielectric layer and the metal gate, including a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, with the top surface of the work function metal layer lower than the high-k dielectric and low resistance metal layers, and a dummy contact plug between gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long wires or metal interconnections are used to connect DDICs to display module, then the connection is established, but space consumption increases and mounting difficulty increases
Solution Approach 1:
The patent merges the driver circuit (DDIC) and display module into a single integrated device, eliminating the need for long external wire connections. The metal interconnection layers are formed within the same semiconductor substrate, combining previously separate components into one compact unit that reduces space consumption while maintaining reliable electrical connections.
Solution Approach 2:
The patent transitions from a planar layout with long wire connections to a three-dimensional integrated structure with multiple metal interconnection layers stacked vertically. This dimensional change allows connections to be made through vertical vias and stacked metal layers rather than long horizontal wires, significantly reducing the footprint area while maintaining connection reliability.
2Reliability
If long wires or metal interconnections are used to connect DDICs to display module, then the connection is established, but mounting difficulty increases
Solution Approach 1:
By integrating the DDIC and display module into a single semiconductor device, the patent eliminates the separate mounting of multiple components. The unified structure requires only single-device mounting procedures, significantly simplifying the manufacturing and assembly process while maintaining reliable internal connections through integrated metal interconnections.
Solution Approach 2:
The patent segments the device into distinct functional regions (driver circuit region and display module region) within the same substrate, with clearly defined metal interconnection paths between them. This segmentation allows for standardized manufacturing processes and simplified mounting procedures compared to connecting separate discrete components.
3Reliability
If metal gate with recess and multiple layers is used, then gate control is improved, but manufacturing complexity increases
Solution Approach 1:
The metal gate is segmented into multiple functional layers including the high-k dielectric layer, work function metal layer, and low resistance metal layer, with a recess formed in the high-k dielectric. This segmentation allows each layer to perform its specific function (insulation, work function adjustment, low resistance contact) while maintaining overall gate control performance, and enables standardized deposition processes for each layer.
Solution Approach 2:
The recess is formed in the high-k dielectric layer before depositing the work function metal and low resistance metal layers. This preliminary action prepares the gate structure in advance, allowing subsequent layers to be deposited directly into the pre-formed recess, thereby simplifying the overall manufacturing process despite the multi-layer complexity.
Data Source
AI summary
A semiconductor device includes a metal gate on a substrate, an interlayer dielectric (ILD) layer around the metal gate, and a recess between the ILD layer and the metal gate. Preferably, the metal gate includes a high-k dielectric layer on the substrate, a work function metal (WFM) layer on the high-k dielectric layer, and a low resistance metal layer on the WFM layer, a top surface of the WFM layer is lower than a top surface of the high-k dielectric layer, a top surface of the WFM layer is lower than a top surface of the low resistance metal layer, and the recess is in the WFM layer.