Metal Gate Dummy Structures for Uniform Large-Dimension FET Gates
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Solution Overview
Problem
The challenge in semiconductor manufacturing is controlling the thickness of the gate metal layer in large dimension metal gate FETs due to the CMP dishing effect, leading to nonplanar surfaces and mismatched threshold voltages, which can cause functional failures.
Innovation Solution
Incorporating p-type and n-type dummy structures made of different materials within the metal gate layers in PMOS and NMOS regions, respectively, to mitigate the CMP dishing effect and achieve uniform gate thickness, thereby reducing threshold voltage mismatch and enhancing design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional metal gate structures are used in large dimension FETs, then the manufacturing process is simple, but the CMP dishing effect causes nonplanar surfaces and thickness mismatch
Solution Approach 1:
The patent introduces dummy structures with different materials (e.g., tungsten, cobalt, tantalum) at specific locations within the gate structure. These localized material variations compensate for the CMP dishing effect by creating differential removal rates during chemical mechanical polishing, ensuring uniform gate thickness across the entire gate region despite the large dimension variations.
Solution Approach 2:
The gate structure employs composite materials by combining the primary gate metal layer with dummy structures made of different metallic materials. This composite approach allows the gate to achieve both mechanical integrity and uniform thickness control, as different materials respond differently to CMP processes, enabling precise thickness matching across large gate dimensions.
2Reliability
If gate metal layer thickness is not controlled, then the manufacturing process is simpler, but threshold voltage mismatch occurs leading to functional failures
Solution Approach 1:
The dummy structures are formed and positioned within the gate structure before the final CMP process. This preliminary arrangement of different materials ensures that during CMP, the differential removal rates will automatically compensate for thickness variations, achieving uniform gate thickness and matching threshold voltages before the device is completed.
Solution Approach 2:
The patent changes the material parameters (type, composition, or crystalline structure) of the dummy structures to alter their CMP removal rates. By selecting materials with appropriate removal rate characteristics, the gate thickness can be precisely controlled across large dimensions, ensuring reliable threshold voltage matching and functional performance.
Data Source
AI summary
In accordance with some aspects of the disclosure, a semiconductor structure is provided. The semiconductor structure includes: an active region; and a gate stack disposed on the active region. The gate stack includes: at least one gate dielectric layer disposed on the active region; and a metal gate structure disposed on the at least one gate dielectric layer. The metal gate structure includes: a metal gate layer comprising a first material; and at least one dummy structure disposed in the metal gate layer, the at least one dummy structure extending vertically through an entire thickness of the metal gate structure and comprising a second material. The second material is different from the first material.