Metal Gate Electrode Fabrication via Conductive Pre-Mask Conversion
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Solution Overview
Problem
The replacement of polysilicon gates with metal gates in semiconductor devices increases the number of process operations required, particularly when reducing device scale, due to the need for multiple etching, depositing, and polishing steps.
Innovation Solution
A method for fabricating semiconductor devices involves forming interlayer insulating layers with trenches, creating conductive layers and pre-mask patterns, and using bake processes to convert these patterns into mask patterns, allowing for the formation of metal gate electrodes with varying widths to reduce resistance and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If replacement metal gate process is used to reduce device scale, then device scaling is achieved, but number of process operations increases
Solution Approach 1:
The patent combines multiple process steps into fewer operations by using a single etching process to form both the gate electrode pattern and the interlayer insulating layer pattern simultaneously. The conductive layer is formed once and serves multiple functions, eliminating the need for separate depositing and polishing operations that would otherwise be required for each layer.
Solution Approach 2:
The conductive layer serves multiple functions: it forms the gate electrode, provides electrical connection, and acts as a barrier layer. By making the conductive layer multi-functional, the patent eliminates the need for separate functional layers that would require additional process steps, thereby reducing the total number of operations while achieving device scaling.
2Manufacturing precision
If multiple etching, depositing, and polishing operations are performed, then metal gate structure is formed, but process complexity increases
Solution Approach 1:
The patent merges multiple etching, depositing, and polishing operations into a simplified process sequence. A single etching process forms both the gate electrode pattern and the interlayer insulating layer pattern, eliminating the need for multiple separate operations while maintaining the required manufacturing precision for the metal gate structure.
Solution Approach 2:
The conductive layer is formed in advance with the appropriate thickness and material properties before the etching process. This preliminary formation of the conductive layer with controlled thickness eliminates the need for subsequent polishing operations, as the layer is already prepared with the required specifications for the metal gate structure.
3Reliability
If conductive layer thickness is reduced, then resistance of metal gate electrode is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the material composition and thickness parameters of the conductive layer to optimize electrical performance. By selecting specific materials and controlling the thickness within a defined range, the patent achieves reduced resistance while maintaining manufacturability, balancing electrical performance with fabrication capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the resistance of metal gate electrodes, enhancing the performance and reliability of semiconductor devices by simplifying the fabrication process and maintaining the integrity of the gate structure.
Implementation Method 1
changing the first pre-mask pattern into a first mask pattern through a first bake process
Implementation Method 2
thermally treating the pre-mask film through a second bake process
Data Source
AI summary
A method for making a semiconductor device includes forming a trench in a first layer on a substrate. A conductive layer having a pattern is formed in the trench. A first metal gate electrode is formed on the conductive layer, and a second metal gate electrode is formed on the first metal gate electrode. The first and second metal gate electrodes at least partially conform to the pattern of the conductive layer. Widths of first surfaces of the first and second metal gate electrodes are different from respective widths of second surfaces of the first and second metal gate electrodes as a result of the pattern.