Metal Gate Electrode Fabrication via Selective Dry Etching
Solution Overview
Problem
The challenge in fabricating semiconductor devices with metal gate electrodes is the difficulty in patterning metal layers using photolithography and etching techniques, especially in narrow and deep grooves, which limits the optimization of CMOS integrated circuits and increases electrical resistance, making it hard to achieve optimal threshold voltage characteristics and yield.
Innovation Solution
A method involving the formation of an insulating layer with grooves for N-channel and P-channel MOS transistor regions, followed by a laminated metal layer and a non-photo sensitive planarization layer that is selectively etched using a dry etching process to expose the metal layer in the N-channel region, allowing for the formation of metal gate electrodes with different work functions by using a spin-on hardmask or amorphous carbon layer and an inorganic anti-reflective layer pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and etching technique are used to pattern metal layer, then gate electrode patterning can be achieved, but it becomes difficult to completely remove photoresist layer in narrow and deep grooves
Solution Approach 1:
The patent introduces a planarization layer as an intermediary material between the photoresist and the metal layer. This planarization layer fills the narrow and deep grooves, providing a planar surface that facilitates complete photoresist removal while maintaining precise gate electrode patterning. The planarization layer acts as a mediator that solves the conflict between achieving precise patterning and enabling complete photoresist removal.
2Reliability
If metal layer is used for gate electrodes, then electrical resistance is reduced, but difficulty in patterning increases
Solution Approach 1:
The planarization layer serves as an intermediary that enables metal layer patterning by providing a planar surface for photoresist application and removal. This intermediary structure allows the metal layer to be used for gate electrodes (reducing electrical resistance) while overcoming the patterning difficulty through the planarization assistance.
3Reliability
If photoresist layer is not completely removed in narrow and deep groove, then threshold voltage characteristics optimization is limited
Solution Approach 1:
The planarization layer acts as an intermediary structure that fills the narrow and deep grooves, creating a planar surface that enables complete photoresist removal. This ensures optimal threshold voltage characteristics by preventing photoresist residue that would otherwise limit performance optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of metal gate electrodes with distinct work functions for N-channel and P-channel MOS transistors, improving the electrical resistance and optimizing the characteristics of CMOS integrated circuits while enhancing the yield and reducing the complexity of the patterning process.
Implementation Method 1
The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region
Data Source
AI summary
A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.