Metal Gate Electrode Void Prevention in Semiconductor Manufacturing

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Solution Overview

Problem

During the manufacturing of semiconductor devices with metal gate electrodes, the formation of voids between dummy gate structures with high aspect ratios leads to leakage current issues due to residual metal in these voids, affecting the electrical characteristics of the devices.

Innovation Solution

A method involving the formation of an etch stop layer and a second insulation layer after removing upper portions of dummy gate structures to prevent void formation between the structures, followed by the replacement of dummy gate electrodes with metal gate electrodes, ensuring no voids are present and reducing leakage currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If dummy gate structures with high aspect ratios are formed to fill space between gate electrodes, then the insulation layer can be properly formed, but voids are generated between the dummy gate structures leading to leakage current

Engineering Contradiction:
Improveinsulation layer formationVSAvoidleakage current
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The dummy gate structures are formed preliminarily to occupy space and enable proper insulation layer formation. By preparing these placeholder structures before final gate electrode formation, the process ensures that insulation layers can be deposited uniformly without voids, while the dummy structures are later removed to eliminate any potential leakage paths.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy gate structures serve as temporary elements that are discarded after fulfilling their space-occupying function. They are removed in a dedicated etching step after the insulation layers are formed, eliminating any risk of leakage current while preserving the benefits of having structured placeholders during manufacturing.

Inventive Principle:
Principle #34Discarding and recovering

2Manufacturing precision

If the space between dummy gate structures is filled with insulation layer, then proper insulation is achieved, but residual metal in voids causes leakage current

Engineering Contradiction:
Improveinsulation layer fillingVSAvoidleakage current
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The harmful residual metal causing leakage current is extracted and removed through a dedicated dummy gate removal process. By separating the dummy gate structures from the final device structure and removing them after insulation layer formation, the process eliminates the source of leakage while maintaining the insulation layer integrity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The potential harm of having voids and residual metal is converted into benefit by using the dummy gate structures as intentional placeholders. These structures enable controlled insulation layer deposition and are then systematically removed, transforming what could be defect-prone voids into a controlled manufacturing step that ensures clean, void-free insulation layers.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Ease of manufacture

If dummy gate structures are removed to form trenches, then metal gate electrodes can be formed, but the process complexity increases

Engineering Contradiction:
Improvemetal gate electrode formationVSAvoidmanufacturing process steps
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The manufacturing process is segmented into distinct phases: dummy gate formation, insulation layer deposition, and dummy gate removal. This segmentation allows each step to be optimized independently, with the dummy gate removal being a simple, targeted etching process that creates clean trenches for metal gate electrode formation without affecting other device regions.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8399327B2Methods of manufacturing a semiconductor device
Publication Date: 2013.03.19 SAMSUNG ELECTRONICS CO LTD
  • US8399327B2 patent drawing
  • US8399327B2 patent drawing
  • US8399327B2 patent drawing

AI summary

A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.