Metal Gate Electrode Void Prevention in Semiconductor Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device fabrication, particularly in CMOS technology, the 'gate last' process faces challenges in achieving low gate resistance due to void generation in metal gate electrodes during high-aspect-ratio trench gap filling, leading to device instability and potential failure as feature sizes decrease.
Innovation Solution
The method involves forming a longer trench with a low-aspect-ratio to effectively fill it with multilayer material, removing excess material to create gate electrodes, and isolating them with dielectric material to prevent void formation, maintaining the original work function and threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 'gate last' process is used to replace polysilicon gate electrode with metal gate electrode, then device performance is improved with decreased feature sizes, but voids are generated in the metal gate electrode after metal layer deposition for gap filling of high-aspect-ratio trench, increasing gate resistance and device instability
Solution Approach 1:
The gate electrode structure is divided into multiple segments: a dummy gate electrode formed first, then removed after source/drain regions are formed, allowing the metal gate layer to be deposited without void formation. This segmentation enables the metal gate to be formed in a lower-aspect-ratio trench, preventing voids and reducing gate resistance while maintaining device performance
Solution Approach 2:
A dummy gate electrode is formed in advance before the metal gate layer is deposited. This preliminary structure allows subsequent processing steps to proceed without creating high-aspect-ratio trenches, and the dummy gate is later removed to reveal the properly formed metal gate electrode without voids
2Productivity
If feature sizes are decreased to improve integration density, then manufacturing complexity increases and void formation becomes more likely in metal gate electrodes
Solution Approach 1:
The manufacturing process is segmented into distinct phases: forming dummy gate, forming source/drain regions, removing dummy gate, and forming metal gate. This segmentation allows each step to be optimized independently, reducing overall process complexity despite decreased feature sizes
Solution Approach 2:
The dummy gate electrode serves as an intermediary structure that facilitates the formation of metal gate electrodes at reduced feature sizes. It enables subsequent processing to avoid high-aspect-ratio trench formation, thereby preventing voids while maintaining integration density
Data Source
AI summary
Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.


