Self-Aligned Metal Gate Etch Back Process for Reduced Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fabrication of high-k/metal gate (HK/MG) structures in semiconductor integrated circuits faces challenges due to the small footprint of the metal filling layer, making it difficult for gate contacts to properly land on the metal filling layer, which increases gate contact resistance and reduces the process window for fabrication.
Innovation Solution
The method involves forming a semiconductor device with a metal gate structure where the metal filling layer has a larger footprint than the gate dielectric and work function layers, allowing the gate contact to directly contact the metal filling layer without contacting the gate dielectric or work function layers, thereby reducing gate contact resistance and enlarging the process window for gate contact fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metal filling layer is made with standard footprint size, then the transistor density and switching speed are improved, but the gate contact cannot properly land on the metal filling layer, resulting in high gate contact resistance
Solution Approach 1:
The patent extends the metal filling layer in the lateral dimension beyond the gate dielectric footprint, creating an overlapping region that allows gate contacts to reliably land on the metal filling layer. This dimensional extension solves the landing problem without requiring larger overall device footprint.
Solution Approach 2:
The metal filling layer is deposited and extended before gate contact formation, ensuring that the contact landing area is already prepared and optimized. This preliminary extension of the metal layer facilitates subsequent contact fabrication with lower resistance.
2Reliability
If the metal filling layer footprint is increased to ensure proper contact landing, then gate contact resistance is reduced, but the process window for fabrication becomes smaller
Solution Approach 1:
The patent applies different footprint dimensions to different functional regions: the metal filling layer has an extended footprint in the lateral direction to ensure contact landing, while maintaining appropriate vertical alignment. This localized dimensional differentiation optimizes both contact resistance and process window.
3Productivity
If traditional polysilicon gates are replaced with high-k/metal gates, then transistor density and switching speed are improved, but the metal filling layer footprint becomes too small for proper gate contact landing
Solution Approach 1:
The patent compensates for the reduced metal filling layer footprint in HK/MG structures by extending the layer in the lateral dimension, creating sufficient overlap area for gate contact landing while maintaining the high-k/metal gate architecture benefits.
Data Source
AI summary
A method includes receiving a device having a substrate and a first dielectric layer surrounding a gate trench. The method further includes depositing a gate dielectric layer and a gate work function (WF) layer in the gate trench and forming a hard mask (HM) layer in a space in the gate trench and surrounded by the gate WF layer. The method further includes recessing the gate WF layer such that a top surface of the gate WF layer in the gate trench is below a top surface of the first dielectric layer. After the recessing of the gate WF layer, the method further includes removing the HM layer in the gate trench and depositing a metal layer in the gate trench. The metal layer is in physical contact with a sidewall surface of the gate WF layer that is deposited before the HM layer is formed.