Metal Gate Etch-Back and Selective Deposition for MOS Devices

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Solution Overview

Problem

The formation of metal gates in MOS devices often results in excessive thinning of inter-layer dielectric, leading to the 'gate loss problem' due to multiple etch-back processes required for long-channel and short-channel devices, which complicates the process and reduces predictability.

Innovation Solution

The process involves forming a dummy gate stack, replacing it with a metal gate, and using a protection layer for etch-back and selective deposition, avoiding full filling and planarization, thus maintaining the gate height and simplifying the process by ensuring a homogenous metal layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple etch-back processes are performed for long-channel and short-channel devices, then the metal gates can be recessed to reduce loading effect, but the inter-layer dielectric is thinned excessively causing gate loss

Engineering Contradiction:

Improvemetal gate recessingVSAvoidinter-layer dielectric thickness

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

A protection layer is formed over the inter-layer dielectric before the etch-back process. This protection layer prevents excessive thinning of the inter-layer dielectric during etching, allowing the metal gates to be recessed without causing gate loss. The protection layer is removed after etching is complete.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The protection layer acts as an intermediary element between the etching process and the inter-layer dielectric. It mediates the etching process by being selectively etched first, allowing controlled removal of metal gates while protecting the underlying inter-layer dielectric from excessive thinning.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Shape

If metal layers are fully filled and planarized using CMP, then the surface is flattened, but gate-height loss occurs due to excessive thinning of inter-layer dielectric

Engineering Contradiction:

Improvesurface flatnessVSAvoidgate height

Core Design Contradiction:

ShapeVSManufacturing precision

Solution Approach 1:

Instead of using CMP to planarize the surface, the excess metal layers are removed through a selective etch-back process. This extracts only the necessary portions of metal layers without requiring mechanical polishing that would thin the inter-layer dielectric and cause gate-height loss.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The mechanical CMP process is replaced with a chemical etching process. The etch-back process uses chemical reactions to remove excess metal layers selectively, avoiding the mechanical abrasion that causes inter-layer dielectric thinning and gate-height loss while still achieving the desired surface flatness.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If polysilicon gate electrodes are used with doping operations, then the work function can be adjusted to the band-edge, but carrier depletion effect occurs near gate dielectrics

Engineering Contradiction:

Improvework function adjustmentVSAvoidcarrier depletion effect

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The material composition of the gate electrode is changed from polysilicon to metal layers. This parameter change eliminates the carrier depletion effect while maintaining the ability to adjust work function to the band-edge through selective metal layer deposition and thickness control.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents gate-height loss by avoiding excessive thinning of inter-layer dielectric during Chemical Mechanical Polish (CMP) and ensures a more predictable and controlled formation of metal gates with a homogenous metal material exposure.

Implementation Method 1

The protection layer is etched back using a first etchant, wherein the first etchant selectively etches the protection layer without etching the gate dielectric layer

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

The metal-containing layer is etched back using a second etchant, wherein the second etchant selectively etches the metal-containing layer without etching the gate dielectric layer

Methodology Applied

Scientific EffectEtching:

Implementation Method 3

A conductive material is selectively deposited into the opening, wherein no conductive material is formed over the inter-layer dielectric

Methodology Applied

Scientific EffectSelective deposition:

Data Source

PatentUS11380774B2Etching back and selective deposition of metal gate

Publication Date: 2022.07.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.