Metal Gate Etch Back Using a Sacrificial Layer to Reduce Loading

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Solution Overview

Problem

The metal gate etch back process in semiconductor manufacturing experiences a loading effect due to varying geometries of gate structures, leading to non-uniform etch control and efficiency issues.

Innovation Solution

A method involving a blanket sacrificial layer deposition during the metal gate etch back process to cover pattern-dense and pattern-sparse regions, reducing the loading effect by ensuring uniform etching across gate structures with different geometries.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If gate structures with different geometries are processed in the MGEB process, then device density and performance are improved, but etch uniformity deteriorates due to loading effects

Engineering Contradiction:
Improvedevice densityVSAvoidetch uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A sacrificial layer is introduced as an intermediary material between the etching process and the gate structures. This sacrificial layer is deposited blanket-across the substrate before patterning, and it serves to equalize the etching load across different gate geometry regions. The sacrificial layer is subsequently patterned and removed, having fulfilled its function of enabling uniform etching of the gate structures underneath.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial layer is deposited and patterned in advance before the actual gate etching process. This preliminary action prepares the structure to withstand the loading effects during etching, ensuring that when the gate etching occurs, the underlying structures are protected and the etching conditions are more uniform across different gate geometries.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If blanket sacrificial layer is deposited across gate structures, then loading effect is reduced and etch uniformity is improved, but process complexity increases

Engineering Contradiction:
Improveetch uniformityVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The sacrificial layer serves multiple functions: it acts as an etch stop layer, provides a uniform starting point for subsequent patterning, and equalizes the loading effect across different gate geometries. By consolidating these functions into a single layer, the process complexity is minimized while achieving the desired etch uniformity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The process utilizes changes in material parameters - specifically, the sacrificial layer is made of a material that has different etch selectivity compared to the gate structures and surrounding materials. This parameter change allows the sacrificial layer to be selectively removed or protected during different etching steps, enabling uniform processing without requiring complex process sequences.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances etch uniformity and efficiency by mitigating the loading effect, resulting in consistent processing of gate structures with varying widths and depths.

Implementation Method 1

employing specific plasma etching techniques to selectively etch materials

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS12622043B2Gate etch back with reduced loading effect
Publication Date: 2026.05.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12622043B2 patent drawing
  • US12622043B2 patent drawing
  • US12622043B2 patent drawing

AI summary

A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.