Metal Gate Etch Back Using a Sacrificial Layer for Uniformity
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Solution Overview
Problem
The metal gate etch back (MGEB) process in semiconductor manufacturing faces challenges with etch uniformity due to varying geometries of gate structures, leading to a loading effect that complicates control over the etching process.
Innovation Solution
A blanket sacrificial layer is deposited across the etched gate structures and spacers during the MGEB process, reducing the loading effect by covering pattern-dense and pattern-sparse regions, which allows for more uniform etching by employing specific plasma etching processes and gas mixtures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate structures with varying geometries are etched back, then the etching process completes, but etch uniformity deteriorates due to loading effect
Solution Approach 1:
A sacrificial layer is deposited as an intermediary material between the etch structures and the etching process. This sacrificial layer has different etch selectivity compared to the gate structures, allowing it to be removed preferentially or at a different rate, thereby compensating for the loading effect and improving etch uniformity across structures of varying geometries
Solution Approach 2:
The etching process parameters are changed by introducing a sacrificial layer with different material properties and etch selectivity. This changes the etching dynamics, allowing the process to accommodate varying gate geometries while maintaining uniformity through selective removal rates
2Manufacturing precision
If blanket sacrificial layer is deposited, then loading effect is reduced and etch uniformity improves, but process complexity increases
Solution Approach 1:
The sacrificial layer is deposited in advance before the etching process begins. This preliminary action prepares the structure to withstand the loading effect during etching, allowing uniform etching to proceed without requiring complex real-time adjustments during the etching process itself
3Manufacturing precision
If plasma etching with specific gas mixtures is used, then etch uniformity improves, but process time increases
Solution Approach 1:
The etching process is divided into periodic stages with different gas mixtures. Different gases are introduced at different times to achieve selective etching of the sacrificial layer versus the gate structures, improving uniformity while managing overall process time through staged removal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the height difference between different gate structures, improving etch uniformity and reducing the loading effect, thereby enhancing the MGEB process efficiency and reducing contamination risks.
Implementation Method 1
employing specific plasma etching processes and gas mixtures
Implementation Method 2
plasma etching processes
Implementation Method 3
A blanket sacrificial layer is deposited across the etched gate structures
Implementation Method 4
deposited across the etched gate structures
Data Source
AI summary
A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.