Metal Gate FinFET Fabrication With Reducing Gas Etch-Back Control
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Solution Overview
Problem
The semiconductor industry faces challenges in balancing stress and gate resistance in metal gate FinFETs, leading to degradation in device performance due to low stress and high gate resistance, which affects gate leakage and work function.
Innovation Solution
A method for forming a FinFET device that includes a gate last approach using a high-k gate dielectric and metal gate electrode, with a composite metal layer comprising a barrier layer, work function metal layer, and metal gate, and applying a reducing gas to prevent etch back failure during the CMP process, ensuring proper stress and resistance balance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a metal gate electrode is used in FinFET devices, then device performance is improved with decreased feature sizes, but gate leakage and work function are affected due to stress and resistance imbalance
Solution Approach 1:
The patent uses a composite metal gate electrode structure consisting of multiple metal layers (e.g., tungsten, cobalt, copper) with different properties. This composite structure allows optimization of both mechanical stress and electrical resistance simultaneously, resolving the contradiction between improved device performance at small feature sizes and maintained gate leakage/work function characteristics.
Solution Approach 2:
The patent adjusts physical and chemical parameters of the metal gate electrode including composition ratios, layer thicknesses, and crystal structure phases. By changing these parameters, the stress and resistance characteristics are tuned to achieve optimal balance between device performance improvement and reliability maintenance.
2Stability of the object's composition
If a gate last approach is used with metal gate electrode, then stability of work function metal during processing is improved, but etch back failure occurs during CMP process
Solution Approach 1:
The patent introduces an intermediary material layer between the metal gate electrode and the dielectric layer. This intermediary layer acts as a protective barrier during CMP processing, preventing direct contact between the CMP slurry and the metal gate electrode, thereby avoiding etch back failure while maintaining the stability benefits of the gate last approach.
Solution Approach 2:
The patent applies a protective coating or capping layer on the metal gate electrode before CMP processing. This beforehand cushioning protects the metal surface from chemical attack by CMP slurry, preventing etch back failure while allowing the gate last approach to maintain work function metal stability throughout processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves gate leakage and work function performance by balancing stress and resistance in metal gate FinFETs, enhancing device performance and preventing etch back failures.
Implementation Method 1
applying a reducing gas to prevent etch back failure during the CMP process
Data Source
AI summary
A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.