Metal Gate FinFET Fabrication With Reducing Gas Etch-Back Protection
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Solution Overview
Problem
The semiconductor industry faces challenges in balancing stress and gate resistance in metal gate FinFET devices, leading to degradation in performance due to low stress and high gate resistance, which affects gate leakage and work function.
Innovation Solution
A method for forming a FinFET device involves using a high-k gate dielectric and metal gate electrode, with a gate last approach, including a composite metal layer with a barrier layer, work function metal layer, and metal gate, and applying a reducing gas to prevent etch back failure during the CMP process, ensuring proper stress and resistance balance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate electrode is used in FinFET devices, then device performance is improved, but gate resistance increases and stress decreases
Solution Approach 1:
The patent employs a composite metal gate structure consisting of multiple metal layers with different properties. The first metal layer provides stress control while the second metal layer provides conductivity, creating a composite material solution that simultaneously addresses both the stress and gate resistance issues associated with metal gate FinFET devices.
2Reliability
If a metal gate electrode is used in FinFET devices, then device performance is improved, but stress decreases
Solution Approach 1:
The patent employs a composite metal gate structure consisting of multiple metal layers with different properties. The first metal layer provides stress control while the second metal layer provides conductivity, creating a composite material solution that simultaneously addresses both the stress and gate resistance issues associated with metal gate FinFET devices.
Solution Approach 2:
The patent applies different material properties to different regions of the gate structure. The first metal layer is specifically selected for its stress-inducing properties to provide mechanical stress to the channel, while the second metal layer is selected for its electrical conductivity to reduce gate resistance, thereby optimizing local qualities to address different performance requirements.
3Manufacturing precision
If CMP process is used to form the metal gate, then planarity is achieved, but etch back failure occurs
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary between the metal gate layers and the CMP process. This sacrificial layer protects the underlying structures during CMP, preventing etch back failure while allowing the CMP process to achieve the necessary planarity for subsequent processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves gate leakage and work function performance by maintaining the integrity of the metal gate structure, preventing etch back failure and enhancing the overall performance of the FinFET device.
Implementation Method 1
applying a reducing gas to prevent etch back failure during the CMP process
Data Source
AI summary
A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.