Metal Gate Fill Layer Materials for Low-Resistance GAA Transistors
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Solution Overview
Problem
Conventional gate-all-around (GAA) transistors face challenges with excessive resistance, work function variations, and gate formation margin issues, which degrade device performance and complicate fabrication, especially at smaller technology nodes where channel-to-channel spacings are limited and material optimizations are critical.
Innovation Solution
The introduction of new gate fill metal materials with low resistance, suitable stress effects, and desirable work functions, such as ruthenium (Ru), iridium (Ir), osmium (Os), rhodium (Rh), and nickel (Ni), which provide improved carrier mobility and simplify device structures by integrating work function and fill metal layers, reducing the need for additional layers and enhancing fabrication reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fill metal materials are used in GAA devices, then the fabrication process is simpler, but the device resistance is excessive and performance is degraded
Solution Approach 1:
The patent changes the material parameters by transitioning from conventional fill metals (Cu, Co, W) to low-resistance materials (Ru, Ir, Os, Rh, Mo). This material substitution directly addresses the excessive resistance problem while the tailored work functions and stress effects provide additional performance benefits without significantly complicating the fabrication process
Solution Approach 2:
The patent employs composite material structures by integrating low-resistance fill metal layers with gate dielectric layers and work function metal layers. This composite approach allows optimization of multiple properties simultaneously - low resistance from the fill metal, appropriate work function from the metal layer, and dielectric properties from the gate dielectric, resolving the performance-degradation issue
2Reliability
If conventional GAA device structures are used, then the gate control is improved, but work function variations and gate formation issues occur
Solution Approach 1:
The patent applies local quality by introducing tailored work function metal layers specifically at the gate interface regions where work function control is critical. This localized approach allows precise control of work function in the gate region without affecting other device areas, thereby improving manufacturing precision and reducing work function variations while preserving the gate-all-around control structure
Solution Approach 2:
The patent changes the work function parameter by selecting specific metal materials with predetermined work function values. This material parameter selection enables precise control and uniformity of work function across the gate structure, directly addressing the work function variation problem while maintaining the effective gate control provided by the GAA architecture
3Reliability
If additional layers are added to GAA devices to improve performance, then device performance increases, but fabrication complexity and production costs increase
Solution Approach 1:
The patent applies multi-functionality by selecting fill metal materials that simultaneously provide multiple functions: low electrical resistance for current conduction, tailored work function for gate control, and stress effects for carrier mobility enhancement. This consolidation of multiple functions into a single material layer reduces the number of separate layers needed, thereby simplifying fabrication and reducing production costs while maintaining improved device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These materials significantly reduce resistance, enhance carrier mobility, and simplify device fabrication, leading to improved performance and reliability of GAA devices by addressing the limitations of conventional fill metal materials at small dimensions and eliminating the need for additional layers, thus reducing fabrication costs and complexity.
Implementation Method 1
low resistance fill metal layer material as stressor in metal gates
Implementation Method 2
with tailored work functions and stress effects
Implementation Method 3
with tailored work functions and stress effects
Data Source
AI summary
An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.