Metal Gate Structure Fabrication for FinFETs
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing metal gate structures for nanometer technology process nodes, particularly in achieving reduced gate resistance and controlling etching amounts for both short and long channel Fin FETs, due to the complexity of three-dimensional designs and the need for high-k dielectric materials.
Innovation Solution
A method involving the formation of dummy gate structures, followed by the deposition of conductive layers and insulating layers, with specific etching and recessing processes to create metal gate electrodes, allowing for separate control of etching depths for short and long channel FETs, and the use of different materials for reduced gate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate replacement technologies are used to manufacture metal gate structures, then high-k dielectric materials can be implemented, but gate resistance reduction and etching control become more complex
Solution Approach 1:
The patent divides the gate structure fabrication into separate processes for short channel and long channel FETs. Different etching conditions are applied to different regions, allowing independent optimization of etching depth and gate resistance for each channel type without compromising the other.
Solution Approach 2:
The patent implements region-specific etching parameters where short channel FETs receive one set of etching conditions and long channel FETs receive another. This local differentiation enables precise control over gate resistance and etching depth in each region, resolving the complexity of uniform processing.
2Manufacturing precision
If uniform etching is applied to both short and long channel FETs, then process simplicity is maintained, but precise control over etching depth and gate resistance is lost
Solution Approach 1:
The patent segments the etching process into at least two distinct etching operations with different parameters. The first etching process targets short channel FETs with specific depth control, while subsequent processes address long channel FETs, enabling precise manufacturing control.
Solution Approach 2:
The patent employs dynamic process adjustment where etching parameters (such as power, gas flow, or chemistry) are changed between or during etching steps to adapt to different channel length requirements, achieving precise depth control while maintaining operational flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate resistance and enables precise control over etching processes, improving the manufacturing efficiency and performance of metal gate structures for both short and long channel Fin FETs.
Implementation Method 1
a first conductive layer is formed over the substrate and the dummy gate structure
Implementation Method 2
a first conductive layer is formed over the substrate and the dummy gate structure
Implementation Method 3
an insulating layer is formed over the first conductive layer and the dummy gate structure
Data Source
AI summary
In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.