Metal Gate Semiconductor Device Fin Shape Preservation
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Solution Overview
Problem
The traditional FinFET transistor's fins are prone to deformation during manufacturing processes, leading to device performance degradation due to silicon consumption during thermal oxidation treatments, which affects the effective channel width.
Innovation Solution
A method is introduced where interfacial layers are formed using deposition processes like ALD, CVD, or PVD instead of thermal oxidation, avoiding silicon consumption and maintaining the fin shape, involving the formation of a composite metal layer with specific barrier and work function metals to fill trenches and serve as a gate dielectric and metal gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thermal oxidation treatment is used to form interfacial layer, then silicon consumption occurs, but fin shape is deformed and effective channel width is reduced
Solution Approach 1:
The patent changes the formation method of the interfacial layer from thermal oxidation to deposition process. This parameter change in the manufacturing process eliminates silicon consumption while maintaining the necessary interfacial layer formation, thereby preserving the fin shape precision and effective channel width.
Solution Approach 2:
The patent replaces the thermal oxidation process with a deposition process for forming the interfacial layer. This substitution of the manufacturing mechanism eliminates the harmful silicon consumption effect while achieving the same functional goal of interfacial layer formation without compromising fin shape.
2Loss of substance
If deposition process is used to form interfacial layer, then silicon consumption is avoided, but process complexity increases
Solution Approach 1:
The patent changes the formation method from thermal oxidation to deposition process. While this eliminates silicon consumption, it does introduce a different process complexity. The deposition process parameters (temperature, pressure, material flow) need to be controlled, but this is a standard industrial process that can be integrated into existing manufacturing lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents fin deformation and maintains the original fin profile, ensuring better channel control and device performance by eliminating silicon loss during interfacial layer formation.
Implementation Method 1
the deposition process includes an atomic layer deposition (ALD) process
Implementation Method 2
the deposition process includes an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process
Implementation Method 3
the deposition process includes an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process
Implementation Method 4
the deposition process includes an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process or a sputter deposition process
Data Source
AI summary
A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.