Metal Gate Patterning With Fluorine-Passivated HK Dielectric
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, the integration density of electronic components increases, but this miniaturization introduces challenges such as maintaining device performance and reliability, particularly in the fabrication of multi-gate transistors like FinFETs and gate-all-around devices, where precise control over gate structures and channel regions is crucial.
Innovation Solution
The method involves a multi-step semiconductor fabrication process that includes forming epitaxial layers, patterning fin elements, creating a dummy gate structure, depositing spacer material, forming source/drain features, and ultimately replacing the dummy gate with a high-K/metal gate stack, ensuring precise control over the gate structure and channel regions of multi-gate devices like FinFETs and GAA transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but additional fabrication challenges and reliability issues arise
Solution Approach 1:
The gate structure is segmented into multiple layers including a sacrificial gate, spacers, and a final metal gate. This segmentation allows each component to be formed and controlled independently, enabling precise control over channel width and gate dimensions even as feature sizes are reduced, thereby maintaining reliability while improving integration density
Solution Approach 2:
A sacrificial gate structure is formed preliminarily to define the channel region before the actual metal gate is created. Spacers are then formed on the sacrificial gate to precisely define the gate width. This preliminary action sequence allows for accurate dimensional control at scaled dimensions, addressing reliability concerns while enabling higher integration density
2Productivity
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but manufacturing complexity increases
Solution Approach 1:
The sacrificial gate structure serves multiple functions: it defines the channel region, provides a template for spacer formation, and is later removed to create the final gate structure. This multi-functionality reduces the number of separate process steps needed, simplifying the overall fabrication process while enabling complex multi-gate structures with high integration density
Solution Approach 2:
The sacrificial gate acts as an intermediary structure that facilitates the formation of the final metal gate. It provides a temporary framework that guides spacer deposition and subsequent etching processes. This intermediary approach simplifies the fabrication of complex gate structures by breaking down the process into manageable steps, reducing overall manufacturing complexity while achieving high integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enhances the performance and reliability of multi-gate transistors by allowing for precise control over gate structures and channel regions, improving device performance and integration density while addressing the challenges of miniaturization.
Implementation Method 1
depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material
Implementation Method 2
depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material
Implementation Method 3
utilizing epitaxial layers and spacer materials to define channel regions, and forming source/drain features through epitaxial growth
Data Source
AI summary
Disclosed is a method of forming gate structures for n-type and p-type transistors. The method includes: forming an interfacial layer and high-K (HK) dielectric layer for the gate structures; forming an n-type metal layer over the HK dielectric layer; forming a hard capping layer over the n-type metal layer while simultaneously strengthening the HK dielectric layer by fluorine passivation; patterning photo resist (PR) material over the hard capping layer that exposes a portion of the hard capping layer over the p-type transistor; removing the n-type metal layer and the hard capping layer over the p-type transistor via wet etching operations using high selectivity chemicals that are highly selective to the hard capping layer and the n-type metal layer; removing the patterned PR material while insulating, by the hard capping layer, gate structures from aluminum oxidation; and forming a p-type metal layer over the hard capping layer and the p-type transistor.