Replacement Metal Gate Structure With Doped TiN Halide Barrier
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Solution Overview
Problem
The diffusion of halide by-products from tungsten CVD deposition into the underlying gate dielectric layer in metal gate structures degrades the gate dielectric material, leading to threshold voltage variation and dielectric leakage, which affects the reliability of FinFET devices.
Innovation Solution
Introducing dopants into the work function metal layer to block the diffusion of halide by-products into the gate dielectric layer, thereby preventing degradation and enhancing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tungsten CVD deposition is performed to form the gate electrode layer, then the gate electrode is successfully formed, but halide by-products diffuse into the gate dielectric layer causing degradation
Solution Approach 1:
A titanium nitride (TiN) layer is introduced as an intermediary barrier between the gate dielectric layer and the tungsten gate electrode layer. This TiN layer prevents halide by-products generated during tungsten CVD deposition from diffusing into the gate dielectric layer, while still allowing the tungsten layer to function as an effective gate electrode. The intermediary layer thus protects the gate dielectric from chemical contamination without compromising device functionality.
Solution Approach 2:
The patent converts the harmful halide by-products generated during tungsten CVD deposition into a beneficial protective mechanism. By intentionally allowing the TiN layer to be exposed to these halide by-products, the TiN layer becomes saturated or passivated, forming a protective barrier that prevents further diffusion of halides into the gate dielectric layer. The harmful by-products thus serve to activate or strengthen the protective function of the TiN layer.
2Reliability
If a metal gate structure with high-k gate dielectric is manufactured, then device performance is improved, but fabrication challenges increase
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a high-k gate dielectric layer for enhanced capacitance, a titanium nitride (TiN) intermediary layer for chemical protection, and a tungsten gate electrode layer for electrical functionality. This segmentation allows each layer to be optimized independently for its specific function while simplifying the overall fabrication process by addressing contamination issues at a specific interface rather than requiring complex process modifications throughout the entire manufacturing flow.
3Device complexity
If the gate electrode layer is deposited directly on the gate dielectric layer, then the structure is simpler, but halide diffusion degrades the dielectric material
Solution Approach 1:
Instead of making the entire gate structure more complex, the patent applies a localized solution by introducing the TiN layer only at the critical interface between the gate dielectric and gate electrode. This local modification provides precise protection against halide diffusion exactly where it is needed, without unnecessarily complicating other portions of the device structure or fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of dopants in the work function metal layer effectively prevents halide by-products from reaching the gate dielectric layer, maintaining the integrity of the gate dielectric material and improving the performance and reliability of FinFET devices.
Implementation Method 1
The diffusion of halide by-products from tungsten CVD deposition into the underlying gate dielectric layer
Implementation Method 2
depositing a gate dielectric layer over bottom and sidewalls of the opening and over the inter-layer dielectric layer
Implementation Method 3
forming a doped work function material layer using an in-situ doping process
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a dummy gate structure over a semiconductor fin. The dummy gate structure includes a dummy gate stack and gate spacers along sidewalls of the dummy gate stack. The method further includes forming an inter-layer dielectric (ILD) layer surrounding the dummy gate structure, removing the dummy gate stack to provide an opening exposing a channel region of the semiconductor fin, depositing a gate dielectric layer over bottom and sidewalls of the opening and over the ILD layer, forming a doped work function material layer over the gate dielectric layer using an in-situ doping process, and depositing a gate electrode layer over the doped work function material layer.