Replacement Metal Gate Stack with Halide Diffusion Blocking

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Solution Overview

Problem

In the fabrication of FinFETs, the diffusion of halide by-products from tungsten CVD deposition into the underlying gate dielectric layer degrades the gate dielectric material, leading to threshold voltage variations and dielectric leakage, reducing device reliability.

Innovation Solution

Introducing dopants into the work function metal layer to occupy diffusion routes and block halide by-products from reaching the gate dielectric layer, thereby preventing degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If tungsten CVD deposition is used to form the gate electrode layer, then the gate electrode can be successfully deposited, but halide by-products diffuse into the gate dielectric layer causing degradation

Engineering Contradiction:
Improvegate electrode depositionVSAvoidgate dielectric integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A titanium nitride layer is introduced as an intermediary between the gate dielectric layer and the tungsten gate electrode layer. This intermediate layer serves as a diffusion barrier that blocks halide by-products from the tungsten CVD deposition from reaching and degrading the gate dielectric layer, while still allowing the tungsten electrode to be successfully deposited.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The titanium nitride layer is formed in advance before the tungsten gate electrode deposition. This preliminary action establishes a protective barrier that prevents the subsequent harmful diffusion of halide by-products during the tungsten deposition process, rather than attempting to repair damage after it occurs.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If the dummy gate stack is removed to form the metal gate, then the metal gate structure can be formed, but the gate dielectric layer becomes exposed and vulnerable to degradation

Engineering Contradiction:
Improvemetal gate formationVSAvoidgate dielectric exposure to halide by-products
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The titanium nitride layer acts as a protective intermediary that remains in place after dummy gate removal. It shields the exposed gate dielectric layer from halide by-products during subsequent tungsten deposition, enabling metal gate formation without compromising dielectric integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The titanium nitride layer provides beforehand cushioning by being present before the harmful deposition process begins. It anticipates and prevents the potential damage from halide by-products, creating a protective buffer that allows the manufacturing process to proceed safely.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The introduction of dopants in the work function metal layer effectively blocks halide by-products, enhancing the reliability and performance of FinFETs by preventing gate dielectric degradation and maintaining consistent device operation.

Implementation Method 1

the diffusion of halide by-products from tungsten CVD deposition into the underlying gate dielectric layer

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS11769669B2Replacement metal gate device structure and method of manufacturing same
Publication Date: 2023.09.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11769669B2 patent drawing
  • US11769669B2 patent drawing
  • US11769669B2 patent drawing

AI summary

The semiconductor device includes a semiconductor fin, and a gate stack over the semiconductor fin. The gate stack includes a gate dielectric layer over a channel region of the semiconductor fin, a work function material layer over the gate dielectric layer, wherein the work function material layer includes dopants, and a gate electrode layer over the work function material layer. The gate dielectric layer is free of the dopants.